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Tue, 18 Nov 2025 00:17:26 -0800 Date: Tue, 18 Nov 2025 00:17:24 -0800 From: Nicolin Chen To: "Tian, Kevin" CC: "joro@8bytes.org" , "afael@kernel.org" , "bhelgaas@google.com" , "alex@shazbot.org" , "jgg@nvidia.com" , "will@kernel.org" , "robin.murphy@arm.com" , "lenb@kernel.org" , "baolu.lu@linux.intel.com" , "linux-arm-kernel@lists.infradead.org" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "linux-acpi@vger.kernel.org" , "linux-pci@vger.kernel.org" , "kvm@vger.kernel.org" , "patches@lists.linux.dev" , "Jaroszynski, Piotr" , "Sethi, Vikram" , "helgaas@kernel.org" , "etzhao1900@gmail.com" Subject: Re: [PATCH v5 5/5] pci: Suspend iommu function prior to resetting a device Message-ID: References: Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D7:EE_|IA0PR12MB8205:EE_ X-MS-Office365-Filtering-Correlation-Id: 950c08ff-ef52-4026-6bf4-08de267af38b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|1800799024|36860700013; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2025 08:17:44.5813 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 950c08ff-ef52-4026-6bf4-08de267af38b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D7.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8205 On Tue, Nov 18, 2025 at 07:53:27AM +0000, Tian, Kevin wrote: > > From: Nicolin Chen > > And how do you think of the followings? > > > > /* > > * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software disables ATS > > before > > * initiating a reset. Though not all IOMMU drivers calls pci_enable_ats(), it > > * only gets invoked in IOMMU driver. And it is racy to check dev- > > >ats_enabled > > * here, as a concurrent IOMMU attachment can enable ATS right after this > > line. > > * > > * Notify the IOMMU driver to stop IOMMU translations until the reset is > > done, > > * to ensure that the ATS function and its related invalidations are disabled. > > */ > > > > I'd remove the words between "Though not ..." and "after this line", which > could be explained in iommu side following Bjorn's suggestion to not check > pci_ats_supported() in pci core. OK. Thanks! Nicolin