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[34.76.60.220]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f85a2573csm25874209f8f.0.2026.07.24.12.30.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 12:30:43 -0700 (PDT) Date: Fri, 24 Jul 2026 19:30:39 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: iommu@lists.linux.dev, "Joerg Roedel (AMD)" , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, Robin Murphy , Will Deacon , David Matlack , Pasha Tatashin , patches@lists.linux.dev, Pranjal Shrivastava , Samiullah Khawaja Subject: Re: [PATCH 6/7] iommu/arm-smmu-v3: Use the generic iommu page table Message-ID: References: <0-v1-807e2d1a5efb+e1-iommupt_armv8_jgg@nvidia.com> <6-v1-807e2d1a5efb+e1-iommupt_armv8_jgg@nvidia.com> Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <6-v1-807e2d1a5efb+e1-iommupt_armv8_jgg@nvidia.com> On Mon, Jul 06, 2026 at 01:29:12PM -0300, Jason Gunthorpe wrote: > Switch to use the iommupt provided page table. This is fairly > straightforward now since the page table construction and hwinfo are very > similar to io-pgtable-arm. > > The struct pt_iommu_armv8_hw_info is a direct replacement for 'tcr' and I > have a kunit compare test validating that the fields have identical values > for identical configurations. > > Quirks are replaced by features > IO_PGTABLE_QUIRK_ARM_HD -> PT_FEAT_ARMV8_DBM > IO_PGTABLE_QUIRK_ARM_S2FWB -> PT_FEAT_ARMV8_S2FWB > > SMMU features are mapped to iommupt features: > ARM_SMMU_FEAT_COHERENCY -> PT_FEAT_DMA_INCOHERENT > ARM_SMMU_FEAT_VAX -> PT_FEAT_ARMV8_LVA > ARM_SMMU_FEAT_S2FWB -> PT_FEAT_ARMV8_S2FWB > > Remove the iommu_flush_ops entirely, iommupt only uses gathers for > invalidation. Wire the tlbi directly to the gather. > > Remove the trampoline for map/unmap/iova/read_and_clear_dirt. iommupt > directly provides the domain ops. Domain initialization is largely moved > into iommupt common code. > > Change the kunit to fully create a page table to generate the tcr bits for > testing. > > Compared to io-pgtable-arm iommupt has a number of key differences: > - CONT support, including always using RIL to avoid errata 3673557 > - Unmap yields a single gather which generates a single tlbi operation > * free_list is always used to free after invalidate > * walk cache and leaf invalidation are combined for non-RIL cases > instead of being duplicated > * non-RIL cut over to all-invalidate covers walk invalidation now too, > umap -> single gather -> single all invalidate. > * RIL flushes the walk cache and leafs together with a good TTL hint. > * RIL always generates one command from any gather. > > Signed-off-by: Jason Gunthorpe > --- > drivers/iommu/arm/Kconfig | 4 +- > .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 45 +-- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 256 ++++++------------ > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 11 +- > 4 files changed, 110 insertions(+), 206 deletions(-) > [...] > - > static bool arm_smmu_dbm_capable(struct arm_smmu_device *smmu) > { > u32 features = (ARM_SMMU_FEAT_HD | ARM_SMMU_FEAT_COHERENCY); > @@ -2831,7 +2785,6 @@ static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap) > case IOMMU_CAP_ENFORCE_CACHE_COHERENCY: > return arm_smmu_master_canwbs(master); > case IOMMU_CAP_NOEXEC: > - case IOMMU_CAP_DEFERRED_FLUSH: Why this is removed? That would drop support for FQ domains. Thanks, Mostafa > return true; > case IOMMU_CAP_DIRTY_TRACKING: > return arm_smmu_dbm_capable(master->smmu);