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[34.142.211.105]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2df913dbc34sm39183265ad.13.2026.09.28.04.35.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 04:35:12 -0700 (PDT) Date: Mon, 28 Sep 2026 11:35:04 +0000 From: Pranjal Shrivastava To: Jason Gunthorpe Cc: Catalin Marinas , Jonathan Corbet , iommu@lists.linux.dev, "Joerg Roedel (AMD)" , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, Mark Rutland , Randy Dunlap , Robin Murphy , Shuah Khan , Will Deacon , David Matlack , Jean-Philippe Brucker , Jonathan Cameron , Nicolin Chen , Pasha Tatashin , patches@lists.linux.dev, Samiullah Khawaja , Mostafa Saleh , stable@vger.kernel.org, Vijayanand Jitta Subject: Re: [PATCH v7 1/9] iommu/arm-smmu-v3: Handle ARM erratum for CONT under invalidation with SVA Message-ID: References: <0-v7-e84261bbe7cd+2ea80b-smmu_tlbi_jgg@nvidia.com> <1-v7-e84261bbe7cd+2ea80b-smmu_tlbi_jgg@nvidia.com> Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1-v7-e84261bbe7cd+2ea80b-smmu_tlbi_jgg@nvidia.com> On Mon, Sep 21, 2026 at 08:55:09PM -0300, Jason Gunthorpe wrote: > The erratum (MMU-700: #3777127, S3: #3673557) deals with under > invalidation of a CONT PTE grouping in the SMMU. The recommended work > around is to use a range invalidation that spans the entire CONT. The only > user of CONT in the kernel right now is through SVA sharing a CPU page > table that contains a CONT created by the mm. > > Previously it was thought that this errata was dealt with because the > driver always uses range invalidation. However, there is a subtle detail > in the errata that the invalidation range must fully enclose the entire > CONT for it to work. > > It seems that two sequential range invalidations, with a split point > falling inside a CONT grouping, will not prevent the errata. > > The SMMU's range invalidation generation algorithm does not produce a > single invalidation for a single SVA invalidation request, nor does the mm > carefully align the SVA invalidation ranges to accommodate the splitting > of the invalidation into several ranges. > > Thus, when processing a SVA invalidation, the range invalidation splitting > routine can generate a range invalidation that is split in the middle of > the CONT and risk under invalidation from this errata. This condition > could be triggered by a malicious userspace manipulating the TLB gathers > via mmap/mprotect/munmap. > > Update the errata list to the include the S3 variation, detect the IOMMUs > that have it, and then have SVA invalidations use a simplified version of > the over invalidation algorithm from the tlbi rework series. This ensures > that a single range invalidation is issued for a single MMU notifier > callback and now the range invalidation is guarenteed to cover any posible > CONT. > > Future work to add CONT to iommu_domain page tables should either use this > one-invalidate/one-range invalidation algorithm or disable CONT support in > the iommu_domain. > > Cc: stable@vger.kernel.org > Cc: Vijayanand Jitta > Fixes: 3f1ce8e85ee0 ("iommu/arm-smmu-v3: Share process page tables") > Reviewed-by: Mostafa Saleh > Tested-by: Nicolin Chen > Signed-off-by: Jason Gunthorpe > --- > Documentation/arch/arm64/silicon-errata.rst | 3 +- > .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 7 ++ > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 91 +++++++++++++++---- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 5 + > 4 files changed, 88 insertions(+), 18 deletions(-) > Reviewed-by: Pranjal Shrivastava Thanks, Praan