From: Jingoo Han <jg1.han@samsung.com>
To: 'Kishon Vijay Abraham I' <kishon@ti.com>, linux-pci@vger.kernel.org
Cc: 'Pratyush Anand' <pratyush.anand@st.com>,
'Mohit KUMAR' <mohit.kumar@st.com>,
'Ajay KHANDELWAL' <ajay.khandelwal@st.com>,
'Jingoo Han' <jg1.han@samsung.com>
Subject: Re: [QUERY] Number of address translation regions in designware
Date: Tue, 22 Oct 2013 14:16:00 +0900 [thread overview]
Message-ID: <000001cecee5$cbeafa10$63c0ee30$%han@samsung.com> (raw)
In-Reply-To: <52652BF1.4040507@ti.com>
On Monday, October 21, 2013 10:28 PM, Kishon Vijay Abraham I wrote:
>
> Currently I see in pcie-designware.c we use only 2 ATU regions. We re-use
> INDEX0 for mem outbound and cfg0, and INDEX1 for cfg1 and io. So I'd like to
> know if in your platform, do you have only 2 address translation regions? In
> DRA7xx we have 16 outbound regions and 4 inbound regions.
In Exynos, there are only 2 inbound and 2 outbound viewpoints.
> Also the same designware IP can be used as a EP also no? Shouldn't we move it
> out of drivers/pci/host and allow it to be configured as EP also?
Currently, Exynos PCIe IP does not support EP mode.
Best regards,
Jingoo Han
next prev parent reply other threads:[~2013-10-22 5:16 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-21 13:28 [QUERY] Number of address translation regions in designware Kishon Vijay Abraham I
2013-10-22 4:36 ` Pratyush Anand
2013-10-22 5:16 ` Jingoo Han [this message]
2013-10-22 14:20 ` Kishon Vijay Abraham I
2013-10-23 4:36 ` Pratyush Anand
2013-10-23 15:45 ` Kishon Vijay Abraham I
2013-10-29 7:10 ` Pratyush Anand
2013-10-29 10:55 ` Kishon Vijay Abraham I
2013-10-29 16:14 ` Pratyush Anand
2013-11-06 8:42 ` Kishon Vijay Abraham I
2013-11-15 0:40 ` Marek Vasut
2013-11-15 5:28 ` Kishon Vijay Abraham I
2013-11-15 6:13 ` Jingoo Han
2013-11-15 15:37 ` Marek Vasut
2013-11-18 5:46 ` Kishon Vijay Abraham I
2013-11-18 14:43 ` Arnd Bergmann
2013-11-01 12:37 ` Marek Vasut
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