* [PATCH] PCI: designware: Add 8 lanes support
@ 2015-05-13 6:44 Zhou Wang
2015-05-19 23:22 ` Bjorn Helgaas
0 siblings, 1 reply; 5+ messages in thread
From: Zhou Wang @ 2015-05-13 6:44 UTC (permalink / raw)
To: Jingoo Han, Bjorn Helgaas, Mohit Kumar, Arnd Bergmann
Cc: linux-pci, gabriele.paoloni, yuanzhichang, zhangjukuo, liguozhu,
Zhou Wang
This patch adds 8 lanes support. Following suggestion from Arnd, just split
this patch from http://www.spinics.net/lists/linux-pci/msg40467.html
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
---
drivers/pci/host/pcie-designware.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 2e9f84f..4ce0aa5 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -31,6 +31,7 @@
#define PORT_LINK_MODE_1_LANES (0x1 << 16)
#define PORT_LINK_MODE_2_LANES (0x3 << 16)
#define PORT_LINK_MODE_4_LANES (0x7 << 16)
+#define PORT_LINK_MODE_8_LANES (0xf << 16)
#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
@@ -38,6 +39,7 @@
#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
+#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
#define PCIE_MSI_ADDR_LO 0x820
#define PCIE_MSI_ADDR_HI 0x824
@@ -778,6 +780,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
case 4:
val |= PORT_LINK_MODE_4_LANES;
break;
+ case 8:
+ val |= PORT_LINK_MODE_8_LANES;
+ break;
}
dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
@@ -794,6 +799,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
case 4:
val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
break;
+ case 8:
+ val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
+ break;
}
dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] PCI: designware: Add 8 lanes support
@ 2015-05-13 13:23 Jingoo Han
2015-05-13 14:04 ` Pratyush Anand
0 siblings, 1 reply; 5+ messages in thread
From: Jingoo Han @ 2015-05-13 13:23 UTC (permalink / raw)
To: 'Zhou Wang'
Cc: 'Bjorn Helgaas', 'Mohit Kumar',
'Arnd Bergmann', linux-pci, 'Pratyush Anand',
'Gabriele Paoloni', 'Zhichang Yuan',
'Zhang Jukuo', 'Liguozhu'
On Wed, 13 May 2015 14:44:34 +0800, Zhou Wang wrote:
> This patch adds 8 lanes support. Following suggestion from Arnd, just split
> this patch from http://www.spinics.net/lists/linux-pci/msg40467.html
>
> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
+cc: Pratyush Anand
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Best regards,
Jingoo Han
> ---
> drivers/pci/host/pcie-designware.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 2e9f84f..4ce0aa5 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -31,6 +31,7 @@
> #define PORT_LINK_MODE_1_LANES (0x1 << 16)
> #define PORT_LINK_MODE_2_LANES (0x3 << 16)
> #define PORT_LINK_MODE_4_LANES (0x7 << 16)
> +#define PORT_LINK_MODE_8_LANES (0xf << 16)
>
> #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
> #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
> @@ -38,6 +39,7 @@
> #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
> #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
> #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
> +#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
>
> #define PCIE_MSI_ADDR_LO 0x820
> #define PCIE_MSI_ADDR_HI 0x824
> @@ -778,6 +780,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> case 4:
> val |= PORT_LINK_MODE_4_LANES;
> break;
> + case 8:
> + val |= PORT_LINK_MODE_8_LANES;
> + break;
> }
> dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
>
> @@ -794,6 +799,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> case 4:
> val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
> break;
> + case 8:
> + val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
> + break;
> }
> dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
>
> --
> 1.9.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] PCI: designware: Add 8 lanes support
2015-05-13 13:23 [PATCH] PCI: designware: Add 8 lanes support Jingoo Han
@ 2015-05-13 14:04 ` Pratyush Anand
0 siblings, 0 replies; 5+ messages in thread
From: Pratyush Anand @ 2015-05-13 14:04 UTC (permalink / raw)
To: Jingoo Han
Cc: Zhou Wang, Bjorn Helgaas, Mohit Kumar, Arnd Bergmann,
linux-pci@vger.kernel.org, Gabriele Paoloni, Zhichang Yuan,
Zhang Jukuo, Liguozhu
On Wed, May 13, 2015 at 6:53 PM, Jingoo Han <jingoohan1@gmail.com> wrote:
> On Wed, 13 May 2015 14:44:34 +0800, Zhou Wang wrote:
>> This patch adds 8 lanes support. Following suggestion from Arnd, just split
>> this patch from http://www.spinics.net/lists/linux-pci/msg40467.html
>>
>> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
>
> +cc: Pratyush Anand
>
Thanks, looks fine to me as well. So.
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
> Acked-by: Jingoo Han <jingoohan1@gmail.com>
>
> Best regards,
> Jingoo Han
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] PCI: designware: Add 8 lanes support
2015-05-13 6:44 Zhou Wang
@ 2015-05-19 23:22 ` Bjorn Helgaas
2015-05-20 3:03 ` Zhou Wang
0 siblings, 1 reply; 5+ messages in thread
From: Bjorn Helgaas @ 2015-05-19 23:22 UTC (permalink / raw)
To: Zhou Wang
Cc: Jingoo Han, Mohit Kumar, Arnd Bergmann, linux-pci,
gabriele.paoloni, yuanzhichang, zhangjukuo, liguozhu
On Wed, May 13, 2015 at 02:44:34PM +0800, Zhou Wang wrote:
> This patch adds 8 lanes support. Following suggestion from Arnd, just split
> this patch from http://www.spinics.net/lists/linux-pci/msg40467.html
>
> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Applied to pci/host-designware for v4.2, with acks from Jingoo and
Pratyush. Thanks!
> ---
> drivers/pci/host/pcie-designware.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 2e9f84f..4ce0aa5 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -31,6 +31,7 @@
> #define PORT_LINK_MODE_1_LANES (0x1 << 16)
> #define PORT_LINK_MODE_2_LANES (0x3 << 16)
> #define PORT_LINK_MODE_4_LANES (0x7 << 16)
> +#define PORT_LINK_MODE_8_LANES (0xf << 16)
>
> #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
> #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
> @@ -38,6 +39,7 @@
> #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
> #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
> #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
> +#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
>
> #define PCIE_MSI_ADDR_LO 0x820
> #define PCIE_MSI_ADDR_HI 0x824
> @@ -778,6 +780,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> case 4:
> val |= PORT_LINK_MODE_4_LANES;
> break;
> + case 8:
> + val |= PORT_LINK_MODE_8_LANES;
> + break;
> }
> dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
>
> @@ -794,6 +799,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> case 4:
> val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
> break;
> + case 8:
> + val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
> + break;
> }
> dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
>
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] PCI: designware: Add 8 lanes support
2015-05-19 23:22 ` Bjorn Helgaas
@ 2015-05-20 3:03 ` Zhou Wang
0 siblings, 0 replies; 5+ messages in thread
From: Zhou Wang @ 2015-05-20 3:03 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Jingoo Han, Mohit Kumar, Arnd Bergmann, linux-pci,
gabriele.paoloni, yuanzhichang, zhangjukuo, liguozhu
On 2015/5/20 7:22, Bjorn Helgaas wrote:
> On Wed, May 13, 2015 at 02:44:34PM +0800, Zhou Wang wrote:
>> This patch adds 8 lanes support. Following suggestion from Arnd, just split
>> this patch from http://www.spinics.net/lists/linux-pci/msg40467.html
>>
>> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
>
> Applied to pci/host-designware for v4.2, with acks from Jingoo and
> Pratyush. Thanks!
Thanks for the applying and the review from Jingoo and Pratyush.
Best Regards,
Zhou
>
>> ---
>> drivers/pci/host/pcie-designware.c | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
>> index 2e9f84f..4ce0aa5 100644
>> --- a/drivers/pci/host/pcie-designware.c
>> +++ b/drivers/pci/host/pcie-designware.c
>> @@ -31,6 +31,7 @@
>> #define PORT_LINK_MODE_1_LANES (0x1 << 16)
>> #define PORT_LINK_MODE_2_LANES (0x3 << 16)
>> #define PORT_LINK_MODE_4_LANES (0x7 << 16)
>> +#define PORT_LINK_MODE_8_LANES (0xf << 16)
>>
>> #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
>> #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
>> @@ -38,6 +39,7 @@
>> #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
>> #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
>> #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
>> +#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
>>
>> #define PCIE_MSI_ADDR_LO 0x820
>> #define PCIE_MSI_ADDR_HI 0x824
>> @@ -778,6 +780,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>> case 4:
>> val |= PORT_LINK_MODE_4_LANES;
>> break;
>> + case 8:
>> + val |= PORT_LINK_MODE_8_LANES;
>> + break;
>> }
>> dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
>>
>> @@ -794,6 +799,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>> case 4:
>> val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
>> break;
>> + case 8:
>> + val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
>> + break;
>> }
>> dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
>>
>> --
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
> .
>
^ permalink raw reply [flat|nested] 5+ messages in thread
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2015-05-13 13:23 [PATCH] PCI: designware: Add 8 lanes support Jingoo Han
2015-05-13 14:04 ` Pratyush Anand
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2015-05-13 6:44 Zhou Wang
2015-05-19 23:22 ` Bjorn Helgaas
2015-05-20 3:03 ` Zhou Wang
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