From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mailout4.samsung.com ([203.254.224.34]:65404 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755088Ab3GKBg6 (ORCPT ); Wed, 10 Jul 2013 21:36:58 -0400 From: Jingoo Han To: 'Kishon Vijay Abraham I' Cc: 'Bjorn Helgaas' , linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, 'Kukjin Kim' , 'Pratyush Anand' , 'Mohit KUMAR' , 'Arnd Bergmann' , 'Sean Cross' , 'SRIKANTH TUMKUR SHIVANAND' , linux-kernel@vger.kernel.org, Jingoo Han References: <000201ce7959$bf0fb150$3d2f13f0$@samsung.com> <51DD695C.6060209@ti.com> In-reply-to: <51DD695C.6060209@ti.com> Subject: Re: [PATCH] pci: exynos: split into two parts such as Synopsys part and Exynos part Date: Thu, 11 Jul 2013 10:36:55 +0900 Message-id: <000b01ce7dd7$20be5bf0$623b13d0$@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii Sender: linux-pci-owner@vger.kernel.org List-ID: On Wednesday, July 10, 2013 11:02 PM, Kishon Vijay Abraham I: > On Friday 05 July 2013 01:59 PM, Jingoo Han wrote: > > Exynos PCIe IP consists of Synopsys specific part and Exynos > > specific part. Only core block is a Synopsys designware part; > > other parts are Exynos specific. > > Also, the Synopsys designware part can be shared with other > > platforms; thus, it can be split two parts such as Synopsys > > designware part and Exynos specific part. > > Thanks for doing that :-) > > I'll be using the synopsys specific part as Jacinto6 also uses the same pcie > core. Once I start implementing, I'll have some queries and comments ;-) Hi Kishon, OK, I see. I will send v2 patch. Also, I will be CC'ing you. :) Best regards, Jingoo Han