linux-pci.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: "Jingoo Han" <jingoohan1@gmail.com>
To: "'Song Xiaowei'" <songxiaowei@hisilicon.com>,
	<bhelgaas@google.com>, <kishon@ti.com>, <arnd@arndb.de>,
	<tn@semihalf.com>, <keith.busch@intel.com>,
	<niklas.cassel@axis.com>, <dhdang@apm.com>,
	<liudongdong3@huawei.com>
Cc: <puck.chen@hisilicon.com>, <guodong.xu@linaro.org>,
	<wangbinghui@hisilicon.com>, <suzhuangluan@hisilicon.com>,
	<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>
Subject: Re: [PATCH 2/3] PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC
Date: Thu, 18 May 2017 14:28:57 -0400	[thread overview]
Message-ID: <001801d2d004$9dfa7850$d9ef68f0$@gmail.com> (raw)
In-Reply-To: <20170515115523.126970-1-songxiaowei@hisilicon.com>

On Monday, May 15, 2017 7:55 AM, Song Xiaowei wrote
> 
> Hisilicon PCIe Driver shares the common functions fo PCIe dw-host
> 
> The poweron functions is developed on hi3660 SoC, while Others Functions
> are common for Kirin series SoCs.
> 
> Lowpower(L1ss and SR), hotplug and MSI feature are not supported

How about 'Low power mode', instead of 'Lowpower'?

'L1ss' is L1 sub state. Then, what is 'SR'?

> currently.
> 
> Cc: Guodong Xu <guodong.xu@linaro.org>
> Signed-off-by: Song Xiaowei <songxiaowei@hisilicon.com>
> ---
>  drivers/pci/dwc/Kconfig      |  10 +
>  drivers/pci/dwc/Makefile     |   1 +
>  drivers/pci/dwc/pcie-kirin.c | 522
> +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 533 insertions(+)
>  create mode 100644 drivers/pci/dwc/pcie-kirin.c
> 
> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
> index d2d2ba5b8a68..13e617b78430 100644
> --- a/drivers/pci/dwc/Kconfig
> +++ b/drivers/pci/dwc/Kconfig
> @@ -130,4 +130,14 @@ config PCIE_ARTPEC6
>  	  Say Y here to enable PCIe controller support on Axis ARTPEC-6
>  	  SoCs.  This PCIe controller uses the DesignWare core.
> 
> +config PCIE_KIRIN
> +	depends on OF && ARM64
> +	bool "HiSilicon Kirin series SoCs PCIe controllers"
> +	depends on PCI
> +	select PCIEPORTBUS
> +	select PCIE_DW_HOST
> +	help
> +	  Say Y here if you want PCIe controller support on HiSilicon Kirin
> series SoCs
> +	  kirin960 SoC
> +
>  endmenu
> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
> index a2df13c28798..4bd69bacd4ab 100644
> --- a/drivers/pci/dwc/Makefile
> +++ b/drivers/pci/dwc/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
>  obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
>  obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
>  obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
> +obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
> 
>  # The following drivers are for devices that use the generic ACPI
>  # pci_root.c driver but don't support standard ECAM config access.
> diff --git a/drivers/pci/dwc/pcie-kirin.c b/drivers/pci/dwc/pcie-kirin.c
> new file mode 100644
> index 000000000000..739f72dae16d
> --- /dev/null
> +++ b/drivers/pci/dwc/pcie-kirin.c
> @@ -0,0 +1,522 @@
> +/*
> + * PCIe host controller driver for Kirin Phone SoCs
> + *
> + * Copyright (C) 2015 Hilisicon Electronics Co., Ltd.

You sent this patch to mailing list in '2017'.
So, please use 2017, instead of 2015.

> + *		http://www.huawei.com
> + *
> + * Author: Xiaowei Song <songxiaowei@huawei.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/mfd/syscon.h>
> +#include <linux/regmap.h>
> +#include <asm/compiler.h>
> +#include <linux/compiler.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/gpio.h>
> +#include <linux/err.h>
> +#include <linux/interrupt.h>
> +#include <linux/of_gpio.h>
> +#include <linux/pci.h>
> +#include <linux/of_pci.h>
> +#include <linux/platform_device.h>
> +#include <linux/resource.h>
> +#include <linux/types.h>
> +#include <linux/of_address.h>
> +#include <linux/pci_regs.h>
> +#include "pcie-designware.h"

Please re-order these header files in alphabetical order for 'readability'.

Best regards,
Jingoo Han

[....]

  reply	other threads:[~2017-05-18 18:28 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-15 11:55 [PATCH 2/3] PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC Song Xiaowei
2017-05-18 18:28 ` Jingoo Han [this message]
  -- strict thread matches above, loose matches on Subject: below --
2017-05-15  6:27 [PATCH 1/3] arm64: dts: hi3660: add pcie node Song Xiaowei
2017-05-15  6:27 ` [PATCH 2/3] PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC Song Xiaowei
2017-05-15  8:21   ` Niklas Cassel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to='001801d2d004$9dfa7850$d9ef68f0$@gmail.com' \
    --to=jingoohan1@gmail.com \
    --cc=arnd@arndb.de \
    --cc=bhelgaas@google.com \
    --cc=dhdang@apm.com \
    --cc=guodong.xu@linaro.org \
    --cc=keith.busch@intel.com \
    --cc=kishon@ti.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=liudongdong3@huawei.com \
    --cc=niklas.cassel@axis.com \
    --cc=puck.chen@hisilicon.com \
    --cc=songxiaowei@hisilicon.com \
    --cc=suzhuangluan@hisilicon.com \
    --cc=tn@semihalf.com \
    --cc=wangbinghui@hisilicon.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).