From: "Shradha Todi" <shradha.t@samsung.com>
To: "'Bjorn Helgaas'" <helgaas@kernel.org>,
"'Krzysztof Kozlowski'" <krzysztof.kozlowski@linaro.org>
Cc: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-samsung-soc@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>,
<mani@kernel.org>, <lpieralisi@kernel.org>,
<kwilczynski@kernel.org>, <robh@kernel.org>,
<bhelgaas@google.com>, <jingoohan1@gmail.com>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<alim.akhtar@samsung.com>, <vkoul@kernel.org>,
<kishon@kernel.org>, <arnd@arndb.de>, <m.szyprowski@samsung.com>,
<jh80.chung@samsung.com>, <pankaj.dubey@samsung.com>
Subject: RE: [PATCH v3 11/12] PCI: exynos: Add support for Tesla FSD SoC
Date: Tue, 19 Aug 2025 17:09:34 +0530 [thread overview]
Message-ID: <00b501dc10fd$f1fecc10$d5fc6430$@samsung.com> (raw)
In-Reply-To: <20250818182544.GA534647@bhelgaas>
> > > > +static irqreturn_t fsd_pcie_irq_handler(int irq, void *arg)
> > > > +{
> > > > + u32 val;
> > > > + struct exynos_pcie *ep = arg;
> > > > + struct dw_pcie *pci = &ep->pci;
> > > > + struct dw_pcie_rp *pp = &pci->pp;
> > > > +
> > > > + val = readl(ep->elbi_base + FSD_IRQ2_STS);
> > > > + if ((val & FSD_IRQ_MSI_ENABLE) == FSD_IRQ_MSI_ENABLE) {
> > > > + val &= FSD_IRQ_MSI_ENABLE;
> > > > + writel(val, ep->elbi_base + FSD_IRQ2_STS);
> > >
> > > This looks weird because FSD_IRQ_MSI_ENABLE sounds like an *enable*
> > > bit, but here you're treating it as a *status* bit.
> > >
> > > As far as I can tell, you set FSD_IRQ_MSI_ENABLE once at probe-time in
> > > fsd_pcie_msi_init(), then you clear it here in an IRQ handler, and it
> > > will never be set again. That seems wrong; am I missing something?
> >
> > Actually the status IRQ and enable IRQ registers are different offsets
> > but the bit position for MSI remains same in both cases so I just reused
> > the macro.
>
> Ah, that's what I missed, thanks! At probe-time, fsd_pcie_msi_init()
> enables it in FSD_IRQ2_EN. Here you clear it in FSD_IRQ2_STS.
>
> > But I understand that it's confusing so I will add another
> > macro for FSD_IRQ_MSI_STATUS or just rename the macro to
> > FSD_IRQ_MSI to re-use.
>
> Using the same name just because a similar bit happens to be at the
> same position in two different registers is definitely confusing. I
> think it will be better to have two macros, one for FSD_IRQ2_STS and
> another for FSD_IRQ2_EN, e.g.,
>
> #define FSD_IRQ2_STS 0x008
> #define FSD_IRQ2_STS_MSI BIT(17)
> #define FSD_IRQ2_EN 0x018
> #define FSD_IRQ2_EN_MSI BIT(17)
>
> Another question about the test:
>
> if ((val & FSD_IRQ_MSI_ENABLE) == FSD_IRQ_MSI_ENABLE) {
>
> This assumes there are no other bits in FSD_IRQ2_STS that could be
> set. I would have expected a test like this:
>
> if (val & FSD_IRQ_MSI_ENABLE) {
>
Thanks for pointing this out. FSD_IRQ_MSI_ENABLE is a single-bit, so there
is no functional difference in the two statements. I didn't have a specific
reason for using "== FSD_IRQ_MSI_ENABLE".
But I see that "val & FSD_IRQ_MSI_ENABLE" would have been the more
standard way to write this. I will update this for clarity.
> Is there a reason to restrict it to the case when *only*
> FSD_IRQ_MSI_ENABLE is set?
>
> Bjorn
next prev parent reply other threads:[~2025-08-19 11:39 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20250811154648epcas5p4e55cc82e0df7d44ea55e249fef63d5fa@epcas5p4.samsung.com>
2025-08-11 15:46 ` [PATCH v3 00/12] Add PCIe support for Tesla FSD SoC Shradha Todi
[not found] ` <CGME20250811154655epcas5p211bd14152fa48635fc5c1daceb963e71@epcas5p2.samsung.com>
2025-08-11 15:46 ` [PATCH v3 01/12] PCI: exynos: Remove unused MACROs in exynos PCIe file Shradha Todi
[not found] ` <CGME20250811154659epcas5p1874791c7ce4e26a2bd36e24a7be55f51@epcas5p1.samsung.com>
2025-08-11 15:46 ` [PATCH v3 02/12] PCI: exynos: Change macro names to exynos specific Shradha Todi
[not found] ` <CGME20250811154707epcas5p20e96a10de3fffcaaf95861358811446c@epcas5p2.samsung.com>
2025-08-11 15:46 ` [PATCH v3 03/12] PCI: exynos: Reorder MACROs to maintain consistency Shradha Todi
[not found] ` <CGME20250811154711epcas5p1847566b0216447ad0976472dddf096dd@epcas5p1.samsung.com>
2025-08-11 15:46 ` [PATCH v3 04/12] PCI: exynos: Add platform device private data Shradha Todi
[not found] ` <CGME20250811154716epcas5p44980091d5273073b9bf2031572c38376@epcas5p4.samsung.com>
2025-08-11 15:46 ` [PATCH v3 05/12] PCI: exynos: Add resource ops, soc variant and device mode Shradha Todi
2025-08-13 23:07 ` Bjorn Helgaas
2025-08-18 9:21 ` Shradha Todi
[not found] ` <CGME20250811154721epcas5p26c9e2880ca55a470f595d914b4030745@epcas5p2.samsung.com>
2025-08-11 15:46 ` [PATCH v3 06/12] dt-bindings: PCI: Split exynos host into two files Shradha Todi
2025-08-12 6:32 ` Krzysztof Kozlowski
2025-08-18 8:41 ` Shradha Todi
[not found] ` <CGME20250811154725epcas5p428fa3370a32bc2b664a4fd8260078097@epcas5p4.samsung.com>
2025-08-11 15:46 ` [PATCH v3 07/12] dt-bindings: PCI: Add support for Tesla FSD SoC Shradha Todi
2025-08-12 6:37 ` Krzysztof Kozlowski
2025-08-18 8:46 ` Shradha Todi
2025-08-30 3:21 ` Manivannan Sadhasivam
2025-08-30 3:27 ` Manivannan Sadhasivam
[not found] ` <CGME20250811154729epcas5p456ddb0d1ba34b992204f54724b57a401@epcas5p4.samsung.com>
2025-08-11 15:46 ` [PATCH v3 08/12] dt-bindings: phy: Add PCIe PHY support for " Shradha Todi
2025-08-14 8:13 ` Krzysztof Kozlowski
[not found] ` <CGME20250811154734epcas5p1ed075fa71285a5c34c2d319bb01c98ac@epcas5p1.samsung.com>
2025-08-11 15:46 ` [PATCH v3 09/12] phy: exynos: Add platform device private data Shradha Todi
[not found] ` <CGME20250811154738epcas5p1d1202f799c4d950c5d5e7f45e39a51e7@epcas5p1.samsung.com>
2025-08-11 15:46 ` [PATCH v3 10/12] phy: exynos: Add PCIe PHY support for FSD SoC Shradha Todi
2025-09-01 12:11 ` Vinod Koul
[not found] ` <CGME20250811154742epcas5p3276c7c053bedc526d9ce370dda83e195@epcas5p3.samsung.com>
2025-08-11 15:46 ` [PATCH v3 11/12] PCI: exynos: Add support for Tesla " Shradha Todi
2025-08-13 23:07 ` Bjorn Helgaas
2025-08-18 9:30 ` Shradha Todi
2025-08-18 18:25 ` Bjorn Helgaas
2025-08-19 6:34 ` Krzysztof Kozlowski
2025-08-19 11:18 ` Shradha Todi
2025-08-19 11:39 ` Shradha Todi [this message]
2025-08-19 15:07 ` Bjorn Helgaas
2025-08-30 3:54 ` Manivannan Sadhasivam
[not found] ` <CGME20250811154746epcas5p261ba0c811f9dd8748f8f241b76be6525@epcas5p2.samsung.com>
2025-08-11 15:46 ` [PATCH v3 12/12] arm64: dts: fsd: Add PCIe " Shradha Todi
2025-08-12 6:43 ` Krzysztof Kozlowski
2025-08-18 8:54 ` Shradha Todi
2025-08-30 3:58 ` Manivannan Sadhasivam
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