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From: Dave Jiang <dave.jiang@intel.com>
To: Terry Bowman <terry.bowman@amd.com>,
	dave@stgolabs.net, jonathan.cameron@huawei.com,
	alison.schofield@intel.com, dan.j.williams@intel.com,
	bhelgaas@google.com, shiju.jose@huawei.com, ming.li@zohomail.com,
	Smita.KoralahalliChannabasappa@amd.com, rrichter@amd.com,
	dan.carpenter@linaro.org, PradeepVineshReddy.Kodamati@amd.com,
	lukas@wunner.de, Benjamin.Cheatham@amd.com,
	sathyanarayanan.kuppuswamy@linux.intel.com,
	linux-cxl@vger.kernel.org, vishal.l.verma@intel.com,
	alucerop@amd.com, ira.weiny@intel.com
Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v14 14/34] PCI/AER: Report CXL or PCIe bus type in AER trace logging
Date: Wed, 14 Jan 2026 13:56:24 -0700	[thread overview]
Message-ID: <0192da8e-c7f3-42e9-a040-16e32dfaecb5@intel.com> (raw)
In-Reply-To: <20260114182055.46029-15-terry.bowman@amd.com>



On 1/14/26 11:20 AM, Terry Bowman wrote:
> The AER service driver and aer_event tracing currently log 'PCIe Bus Type'
> for all errors. Update the driver and aer_event tracing to log 'CXL Bus
> Type' for CXL device errors.
> 
> This requires that AER can identify and distinguish between PCIe errors and
> CXL errors.
> 
> Introduce boolean 'is_cxl' to 'struct aer_err_info'. Add assignment in
> aer_get_device_error_info() and pci_print_aer().
> 
> Update the aer_event trace routine to accept a bus type string parameter.
> 
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Co-developed-by: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>

Reviewed-by: Dave Jiang <dave.jiang@intel.com>


> 
> ---
> 
> Changes in v13->v14:
> - Merged with Dan's commit. Changes are moving bus_type the last
>   parameter in function calls (Dan)
> - Removed all DCOs because of changes (Terry)
> - Update commit message (Bjorn)
> - Add Bjorn's ack-by
> 
> Changes in v12->v13:
> - Remove duplicated aer_err_info inline comments. Is already in the
>   kernel-doc header (Ben)
> 
> Changes in v11->v12:
>  - Change aer_err_info::is_cxl to be bool a bitfield. Update structure
>  padding. (Lukas)
>  - Add kernel-doc for 'struct aer_err_info' (Lukas)
> 
> Changes in v10->v11:
>  - Remove duplicate call to trace_aer_event() (Shiju)
>  - Added Dan William's and Dave Jiang's reviewed-by
> ---
>  drivers/pci/pci.h       |  8 +++++++-
>  drivers/pci/pcie/aer.c  | 20 +++++++++++++-------
>  include/ras/ras_event.h | 12 ++++++++----
>  3 files changed, 28 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index 0e67014aa001..41ec38e82c08 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -738,7 +738,8 @@ struct aer_err_info {
>  	unsigned int multi_error_valid:1;
>  
>  	unsigned int first_error:5;
> -	unsigned int __pad2:2;
> +	unsigned int __pad2:1;
> +	unsigned int is_cxl:1;
>  	unsigned int tlp_header_valid:1;
>  
>  	unsigned int status;		/* COR/UNCOR Error Status */
> @@ -749,6 +750,11 @@ struct aer_err_info {
>  int aer_get_device_error_info(struct aer_err_info *info, int i);
>  void aer_print_error(struct aer_err_info *info, int i);
>  
> +static inline const char *aer_err_bus(struct aer_err_info *info)
> +{
> +	return info->is_cxl ? "CXL" : "PCIe";
> +}
> +
>  int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2,
>  		      unsigned int tlp_len, bool flit,
>  		      struct pcie_tlp_log *log);
> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
> index b1e6ee7468b9..d30a217fae46 100644
> --- a/drivers/pci/pcie/aer.c
> +++ b/drivers/pci/pcie/aer.c
> @@ -870,6 +870,7 @@ void aer_print_error(struct aer_err_info *info, int i)
>  	struct pci_dev *dev;
>  	int layer, agent, id;
>  	const char *level = info->level;
> +	const char *bus_type = aer_err_bus(info);
>  
>  	if (WARN_ON_ONCE(i >= AER_MAX_MULTI_ERR_DEVICES))
>  		return;
> @@ -879,22 +880,22 @@ void aer_print_error(struct aer_err_info *info, int i)
>  
>  	pci_dev_aer_stats_incr(dev, info);
>  	trace_aer_event(pci_name(dev), (info->status & ~info->mask),
> -			info->severity, info->tlp_header_valid, &info->tlp);
> +			info->severity, info->tlp_header_valid, &info->tlp, bus_type);
>  
>  	if (!info->ratelimit_print[i])
>  		return;
>  
>  	if (!info->status) {
> -		pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n",
> -			aer_error_severity_string[info->severity]);
> +		pci_err(dev, "%s Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n",
> +			bus_type, aer_error_severity_string[info->severity]);
>  		goto out;
>  	}
>  
>  	layer = AER_GET_LAYER_ERROR(info->severity, info->status);
>  	agent = AER_GET_AGENT(info->severity, info->status);
>  
> -	aer_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n",
> -		   aer_error_severity_string[info->severity],
> +	aer_printk(level, dev, "%s Bus Error: severity=%s, type=%s, (%s)\n",
> +		   bus_type, aer_error_severity_string[info->severity],
>  		   aer_error_layer[layer], aer_agent_string[agent]);
>  
>  	aer_printk(level, dev, "  device [%04x:%04x] error status/mask=%08x/%08x\n",
> @@ -928,6 +929,7 @@ EXPORT_SYMBOL_GPL(cper_severity_to_aer);
>  void pci_print_aer(struct pci_dev *dev, int aer_severity,
>  		   struct aer_capability_regs *aer)
>  {
> +	const char *bus_type;
>  	int layer, agent, tlp_header_valid = 0;
>  	u32 status, mask;
>  	struct aer_err_info info = {
> @@ -948,10 +950,13 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity,
>  
>  	info.status = status;
>  	info.mask = mask;
> +	info.is_cxl = pcie_is_cxl(dev);
> +
> +	bus_type = aer_err_bus(&info);
>  
>  	pci_dev_aer_stats_incr(dev, &info);
> -	trace_aer_event(pci_name(dev), (status & ~mask),
> -			aer_severity, tlp_header_valid, &aer->header_log);
> +	trace_aer_event(pci_name(dev), (status & ~mask), aer_severity,
> +			tlp_header_valid, &aer->header_log, bus_type);
>  
>  	if (!aer_ratelimit(dev, info.severity))
>  		return;
> @@ -1301,6 +1306,7 @@ int aer_get_device_error_info(struct aer_err_info *info, int i)
>  	/* Must reset in this function */
>  	info->status = 0;
>  	info->tlp_header_valid = 0;
> +	info->is_cxl = pcie_is_cxl(dev);
>  
>  	/* The device might not support AER */
>  	if (!aer)
> diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h
> index eaecc3c5f772..fdb785fa4613 100644
> --- a/include/ras/ras_event.h
> +++ b/include/ras/ras_event.h
> @@ -339,9 +339,11 @@ TRACE_EVENT(aer_event,
>  		 const u32 status,
>  		 const u8 severity,
>  		 const u8 tlp_header_valid,
> -		 struct pcie_tlp_log *tlp),
> +		 struct pcie_tlp_log *tlp,
> +		 const char *bus_type),
>  
> -	TP_ARGS(dev_name, status, severity, tlp_header_valid, tlp),
> +
> +	TP_ARGS(dev_name, status, severity, tlp_header_valid, tlp, bus_type),
>  
>  	TP_STRUCT__entry(
>  		__string(	dev_name,	dev_name	)
> @@ -349,10 +351,12 @@ TRACE_EVENT(aer_event,
>  		__field(	u8,		severity	)
>  		__field(	u8, 		tlp_header_valid)
>  		__array(	u32, 		tlp_header, PCIE_STD_MAX_TLP_HEADERLOG)
> +		__string(	bus_type,	bus_type	)
>  	),
>  
>  	TP_fast_assign(
>  		__assign_str(dev_name);
> +		__assign_str(bus_type);
>  		__entry->status		= status;
>  		__entry->severity	= severity;
>  		__entry->tlp_header_valid = tlp_header_valid;
> @@ -364,8 +368,8 @@ TRACE_EVENT(aer_event,
>  		}
>  	),
>  
> -	TP_printk("%s PCIe Bus Error: severity=%s, %s, TLP Header=%s\n",
> -		__get_str(dev_name),
> +	TP_printk("%s %s Bus Error: severity=%s, %s, TLP Header=%s\n",
> +		__get_str(dev_name), __get_str(bus_type),
>  		__entry->severity == AER_CORRECTABLE ? "Corrected" :
>  			__entry->severity == AER_FATAL ?
>  			"Fatal" : "Uncorrected, non-fatal",


  parent reply	other threads:[~2026-01-14 20:56 UTC|newest]

Thread overview: 129+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-14 18:20 [PATCH v14 00/34] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2026-01-14 18:20 ` [PATCH v14 01/34] PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h Terry Bowman
2026-01-22 18:58   ` Bjorn Helgaas
2026-01-22 19:43     ` Bowman, Terry
2026-01-14 18:20 ` [PATCH v14 02/34] PCI: Update CXL DVSEC definitions Terry Bowman
2026-01-14 18:53   ` Jonathan Cameron
2026-01-19 23:44     ` dan.j.williams
2026-01-22 18:37   ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 03/34] PCI: Introduce pcie_is_cxl() Terry Bowman
2026-01-21  1:19   ` dan.j.williams
2026-01-22 18:39   ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 04/34] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Terry Bowman
2026-01-14 18:20 ` [PATCH v14 05/34] cxl/pci: Remove unnecessary CXL RCH " Terry Bowman
2026-01-14 18:20 ` [PATCH v14 06/34] PCI: Replace cxl_error_is_native() with pcie_aer_is_native() Terry Bowman
2026-01-14 18:55   ` Jonathan Cameron
2026-01-14 20:16     ` Dave Jiang
2026-01-14 20:15   ` Dave Jiang
2026-01-22 18:23   ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 07/34] cxl/pci: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from core/pci.c Terry Bowman
2026-01-14 20:51   ` Dave Jiang
2026-01-14 18:20 ` [PATCH v14 08/34] cxl/pci: Move CXL driver's RCH error handling into core/ras_rch.c Terry Bowman
2026-01-14 20:35   ` Dave Jiang
2026-01-14 18:20 ` [PATCH v14 09/34] PCI/AER: Export pci_aer_unmask_internal_errors() Terry Bowman
2026-01-14 19:01   ` Jonathan Cameron
2026-01-14 19:09   ` Kuppuswamy Sathyanarayanan
2026-01-14 20:40   ` Dave Jiang
2026-01-20  2:09   ` dan.j.williams
2026-01-22 10:31     ` Lukas Wunner
2026-01-22 16:48       ` dan.j.williams
2026-01-22 18:51         ` Lukas Wunner
2026-01-22 18:49   ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 10/34] PCI/AER: Update is_internal_error() to be non-static is_aer_internal_error() Terry Bowman
2026-01-14 19:08   ` Jonathan Cameron
2026-01-15 20:42     ` dan.j.williams
2026-01-22 13:34       ` Lukas Wunner
2026-01-22 19:09         ` dan.j.williams
2026-01-22 19:32           ` Lukas Wunner
2026-01-22 21:32             ` dan.j.williams
2026-01-23 12:22               ` Jonathan Cameron
2026-01-20  2:20   ` dan.j.williams
2026-01-20 15:15     ` Bowman, Terry
2026-01-20 16:53       ` dan.j.williams
2026-01-22 18:48   ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 11/34] PCI/AER: Move CXL RCH error handling to aer_cxl_rch.c Terry Bowman
2026-01-22 17:23   ` Markus Elfring
2026-01-22 20:05     ` Bowman, Terry
2026-01-22 18:53   ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 12/34] PCI/AER: Use guard() in cxl_rch_handle_error_iter() Terry Bowman
2026-01-14 19:11   ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 13/34] PCI/AER: Replace PCIEAER_CXL symbol with CXL_RAS Terry Bowman
2026-01-14 19:12   ` Jonathan Cameron
2026-01-14 20:49   ` Dave Jiang
2026-01-14 20:50   ` Dave Jiang
2026-01-22 18:24   ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 14/34] PCI/AER: Report CXL or PCIe bus type in AER trace logging Terry Bowman
2026-01-14 19:45   ` Jonathan Cameron
2026-01-15 15:55     ` Mauro Carvalho Chehab
2026-01-14 20:56   ` Dave Jiang [this message]
2026-01-14 18:20 ` [PATCH v14 15/34] PCI/AER: Update struct aer_err_info with kernel-doc formatting Terry Bowman
2026-01-14 19:48   ` Jonathan Cameron
2026-01-15 20:56     ` dan.j.williams
2026-01-14 21:06   ` Dave Jiang
2026-01-22 18:29   ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 16/34] cxl/mem: Clarify @host for devm_cxl_add_nvdimm() Terry Bowman
2026-01-14 19:49   ` Jonathan Cameron
2026-01-14 21:08   ` Dave Jiang
2026-01-16  3:07     ` dan.j.williams
2026-01-16 16:22       ` Dave Jiang
2026-01-14 18:20 ` [PATCH v14 17/34] cxl: Update RAS handler interfaces to also support CXL Ports Terry Bowman
2026-01-14 18:20 ` [PATCH v14 18/34] cxl/port: Remove "enumerate dports" helpers Terry Bowman
2026-01-14 19:50   ` Jonathan Cameron
2026-01-14 21:23     ` Dave Jiang
2026-01-16  3:15     ` dan.j.williams
2026-01-14 21:24   ` Dave Jiang
2026-01-16  3:21   ` dan.j.williams
2026-01-14 18:20 ` [PATCH v14 19/34] cxl/port: Fix devm resource leaks around with dport management Terry Bowman
2026-01-14 21:26   ` Dave Jiang
2026-01-15 14:46   ` Jonathan Cameron
2026-01-16  4:45     ` dan.j.williams
2026-01-16 15:01       ` Jonathan Cameron
2026-01-16 16:16         ` Jonathan Cameron
2026-01-19 23:02           ` dan.j.williams
2026-01-20 12:25             ` Jonathan Cameron
2026-01-19  2:48         ` dan.j.williams
2026-01-14 18:20 ` [PATCH v14 20/34] cxl/port: Move dport operations to a driver event Terry Bowman
2026-01-14 21:45   ` Dave Jiang
2026-01-15 14:56   ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 21/34] cxl/port: Move dport RAS reporting to a port resource Terry Bowman
2026-01-14 21:47   ` Dave Jiang
2026-01-15 15:02   ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 22/34] cxl: Update CXL Endpoint tracing Terry Bowman
2026-01-14 18:20 ` [PATCH v14 23/34] cxl: Map CXL Endpoint Port and CXL Switch Port RAS registers Terry Bowman
2026-01-14 21:53   ` Dave Jiang
2026-01-15 15:17   ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 24/34] cxl/port: Move endpoint component register management to cxl_port Terry Bowman
2026-01-14 21:55   ` Dave Jiang
2026-01-15 15:28   ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 25/34] cxl/port: Map Port component registers before switchport init Terry Bowman
2026-01-14 21:59   ` Dave Jiang
2026-01-15 15:30   ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 26/34] cxl: Change CXL handlers to use guard() instead of scoped_guard() Terry Bowman
2026-01-23 10:05   ` Markus Elfring
2026-01-14 18:20 ` [PATCH v14 27/34] PCI/ERR: Introduce PCI_ERS_RESULT_PANIC Terry Bowman
2026-01-14 18:58   ` Kuppuswamy Sathyanarayanan
2026-01-14 19:20     ` Bowman, Terry
2026-01-14 19:45       ` Kuppuswamy Sathyanarayanan
2026-01-14 18:20 ` [PATCH v14 28/34] PCI/AER: Move AER driver's CXL VH handling to pcie/aer_cxl_vh.c Terry Bowman
2026-01-15 15:40   ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 29/34] cxl/port: Unify endpoint and switch port lookup Terry Bowman
2026-01-14 23:04   ` Dave Jiang
2026-01-15 15:44   ` Jonathan Cameron
2026-01-14 18:20 ` [PATCH v14 30/34] PCI/AER: Dequeue forwarded CXL error Terry Bowman
2026-01-14 23:18   ` Dave Jiang
2026-01-16 14:42     ` Bowman, Terry
2026-01-15 16:01   ` Jonathan Cameron
2026-01-15 17:29     ` Bowman, Terry
2026-01-22 18:32   ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 31/34] PCI: Introduce CXL Port protocol error handlers Terry Bowman
2026-01-14 23:37   ` Dave Jiang
2026-01-15 16:12     ` Jonathan Cameron
2026-01-22 18:27   ` Bjorn Helgaas
2026-01-14 18:20 ` [PATCH v14 32/34] cxl: Update Endpoint uncorrectable protocol error handling Terry Bowman
2026-01-14 22:07   ` dan.j.williams
2026-01-15 15:26     ` Bowman, Terry
2026-01-15 15:27     ` Bowman, Terry
2026-01-14 18:20 ` [PATCH v14 33/34] cxl: Update Endpoint correctable " Terry Bowman
2026-01-14 18:20 ` [PATCH v14 34/34] cxl: Enable CXL protocol errors during CXL Port probe Terry Bowman
2026-01-15 16:18   ` Jonathan Cameron
2026-01-15 19:41     ` Bowman, Terry

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