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Tue, 1 Jul 2025 11:06:04 +0000 (GMT) From: "Shradha Todi" To: "'Rob Herring'" Cc: , , , , , , , , , , , , , , , , , , , , In-Reply-To: <20250627211721.GA153863-robh@kernel.org> Subject: RE: [PATCH v2 07/10] dt-bindings: phy: Add PHY bindings support for FSD SoC Date: Tue, 1 Jul 2025 16:36:03 +0530 Message-ID: <02af01dbea78$24f01310$6ed03930$@samsung.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQFUClgbainc6hQuKSBO0V8ttZVgkwGg1JXJAfs/ltABn1f9rLUC/odg Content-Language: en-in X-CMS-MailID: 20250701110607epcas5p34c04a301caaf7d8c504eca2fec7f3139 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250625165319epcas5p3721c19f6e6b482438c62dd1ef784de03 References: <20250625165229.3458-1-shradha.t@samsung.com> <20250625165229.3458-8-shradha.t@samsung.com> <20250627211721.GA153863-robh@kernel.org> > -----Original Message----- > From: Rob Herring > Sent: 28 June 2025 02:47 > To: Shradha Todi > Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org; linux-phy@lists.infradead.org; linux- > fsd@tesla.com; manivannan.sadhasivam@linaro.org; lpieralisi@kernel.org; kw@linux.com; > bhelgaas@google.com; jingoohan1@gmail.com; krzk+dt@kernel.org; conor+dt@kernel.org; > alim.akhtar@samsung.com; vkoul@kernel.org; kishon@kernel.org; arnd@arndb.de; > m.szyprowski@samsung.com; jh80.chung@samsung.com; pankaj.dubey@samsung.com > Subject: Re: [PATCH v2 07/10] dt-bindings: phy: Add PHY bindings support for FSD SoC > > On Wed, Jun 25, 2025 at 10:22:26PM +0530, Shradha Todi wrote: > > Document PHY device tree bindings for Tesla FSD SoCs. > > > > Signed-off-by: Shradha Todi > > --- > > .../bindings/phy/samsung,exynos-pcie-phy.yaml | 25 +++++++++++++++++-- > > 1 file changed, 23 insertions(+), 2 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml > b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml > > index 41df8bb08ff7..4dc20156cdde 100644 > > --- a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml > > +++ b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml > > @@ -15,10 +15,13 @@ properties: > > const: 0 > > > > compatible: > > - const: samsung,exynos5433-pcie-phy > > + enum: > > + - samsung,exynos5433-pcie-phy > > + - tesla,fsd-pcie-phy > > > > reg: > > - maxItems: 1 > > + minItems: 1 > > + maxItems: 2 > > > > samsung,pmu-syscon: > > $ref: /schemas/types.yaml#/definitions/phandle > > @@ -30,6 +33,24 @@ properties: > > description: phandle for FSYS sysreg interface, used to control > > sysreg registers bits for PCIe PHY > > > > +allOf: > > + - if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - tesla,fsd-pcie-phy > > + then: > > + description: > > + The PHY controller nodes are represented in the aliases node > > + using the following format 'pciephy{n}'. Depending on whether > > + n is 0 or 1, the phy init sequence is chosen. > > What? Don't make up your own aliases. > > If the PHY instances are different, then maybe you need a different > compatible. If this is just selecting the PHY mode, you can do that in > PHY cells as the mode depends on the consumer. > FSD PCIe has 2 instances of PHY. Both are the same HW Samsung PHYs (Therefore share the same register offsets). But the PHY used here does not support auto adaptation so we need to tune the PHYs according to the use case (considering channel loss, etc). This is why we have 2 different SW PHY initialization sequence depending on the instance number. Do you think having different compatible (something like tesla,fsd-pcie-phy0 and tesla,fsd-pcie-phy1) and having phy ID as platform data is okay in this case? I actually took reference from files like: drivers/usb/phy/phy-am335x-control.c drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c who use alias to differentiate between register offsets for instances. > > > + properties: > > + reg: > > + items: > > + - description: PHY > > + - description: PCS > > else: > properties: > reg: > maxItems: 1 > Will update. Thanks for the review! > > + > > required: > > - "#phy-cells" > > - compatible > > -- > > 2.49.0 > >