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Tue, 1 Jul 2025 13:35:16 +0000 (GMT) From: "Shradha Todi" To: "'Krzysztof Kozlowski'" , "'Rob Herring'" Cc: , , , , , , , , , , , , , , , , , , , , In-Reply-To: Subject: RE: [PATCH v2 07/10] dt-bindings: phy: Add PHY bindings support for FSD SoC Date: Tue, 1 Jul 2025 19:05:15 +0530 Message-ID: <02bf01dbea8c$fc835cb0$f58a1610$@samsung.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQFUClgbainc6hQuKSBO0V8ttZVgkwGg1JXJAfs/ltABn1f9rAD4JQ8bAeFf3fS07FvF0A== Content-Language: en-in X-CMS-MailID: 20250701133519epcas5p487e7452860a95fd78fe65dea6781a0f4 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250625165319epcas5p3721c19f6e6b482438c62dd1ef784de03 References: <20250625165229.3458-1-shradha.t@samsung.com> <20250625165229.3458-8-shradha.t@samsung.com> <20250627211721.GA153863-robh@kernel.org> <02af01dbea78$24f01310$6ed03930$@samsung.com> > -----Original Message----- > From: Krzysztof Kozlowski > Sent: 01 July 2025 16:55 > To: Shradha Todi ; 'Rob Herring' > Cc: linux-pci=40vger.kernel.org; devicetree=40vger.kernel.org; linux-arm-= kernel=40lists.infradead.org; linux- > samsung-soc=40vger.kernel.org; linux-kernel=40vger.kernel.org; linux-phy= =40lists.infradead.org; linux- > fsd=40tesla.com; mani=40kernel.org; lpieralisi=40kernel.org; kw=40linux.c= om; bhelgaas=40google.com; > jingoohan1=40gmail.com; krzk+dt=40kernel.org; conor+dt=40kernel.org; alim= .akhtar=40samsung.com; > vkoul=40kernel.org; kishon=40kernel.org; arnd=40arndb.de; m.szyprowski=40= samsung.com; > jh80.chung=40samsung.com; pankaj.dubey=40samsung.com > Subject: Re: =5BPATCH v2 07/10=5D dt-bindings: phy: Add PHY bindings supp= ort for FSD SoC >=20 > On 01/07/2025 13:06, Shradha Todi wrote: > > > > > >> -----Original Message----- > >> From: Rob Herring > >> Sent: 28 June 2025 02:47 > >> To: Shradha Todi > >> Cc: linux-pci=40vger.kernel.org; devicetree=40vger.kernel.org; linux-a= rm-kernel=40lists.infradead.org; > > linux- > >> samsung-soc=40vger.kernel.org; linux-kernel=40vger.kernel.org; linux-p= hy=40lists.infradead.org; linux- > >> fsd=40tesla.com; manivannan.sadhasivam=40linaro.org; lpieralisi=40kern= el.org; kw=40linux.com; > >> bhelgaas=40google.com; jingoohan1=40gmail.com; krzk+dt=40kernel.org; c= onor+dt=40kernel.org; > >> alim.akhtar=40samsung.com; vkoul=40kernel.org; kishon=40kernel.org; ar= nd=40arndb.de; > >> m.szyprowski=40samsung.com; jh80.chung=40samsung.com; pankaj.dubey=40s= amsung.com > >> Subject: Re: =5BPATCH v2 07/10=5D dt-bindings: phy: Add PHY bindings s= upport for FSD SoC > >> > >> On Wed, Jun 25, 2025 at 10:22:26PM +0530, Shradha Todi wrote: > >>> Document PHY device tree bindings for Tesla FSD SoCs. > >>> > >>> Signed-off-by: Shradha Todi > >>> --- > >>> .../bindings/phy/samsung,exynos-pcie-phy.yaml =7C 25 +++++++++++++++= ++-- > >>> 1 file changed, 23 insertions(+), 2 deletions(-) > >>> > >>> diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos-pci= e-phy.yaml > >> b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml > >>> index 41df8bb08ff7..4dc20156cdde 100644 > >>> --- a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.y= aml > >>> +++ b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.y= aml > >>> =40=40 -15,10 +15,13 =40=40 properties: > >>> const: 0 > >>> > >>> compatible: > >>> - const: samsung,exynos5433-pcie-phy > >>> + enum: > >>> + - samsung,exynos5433-pcie-phy > >>> + - tesla,fsd-pcie-phy > >>> > >>> reg: > >>> - maxItems: 1 > >>> + minItems: 1 > >>> + maxItems: 2 > >>> > >>> samsung,pmu-syscon: > >>> =24ref: /schemas/types.yaml=23/definitions/phandle > >>> =40=40 -30,6 +33,24 =40=40 properties: > >>> description: phandle for FSYS sysreg interface, used to control > >>> sysreg registers bits for PCIe PHY > >>> > >>> +allOf: > >>> + - if: > >>> + properties: > >>> + compatible: > >>> + contains: > >>> + enum: > >>> + - tesla,fsd-pcie-phy > >>> + then: > >>> + description: > >>> + The PHY controller nodes are represented in the aliases node > >>> + using the following format 'pciephy=7Bn=7D'. Depending on wh= ether > >>> + n is 0 or 1, the phy init sequence is chosen. > >> > >> What? Don't make up your own aliases. > >> > >> If the PHY instances are different, then maybe you need a different > >> compatible. If this is just selecting the PHY mode, you can do that in > >> PHY cells as the mode depends on the consumer. > >> > > > > FSD PCIe has 2 instances of PHY. Both are the same HW Samsung > > PHYs (Therefore share the same register offsets). But the PHY used here >=20 > So same? >=20 > > does not support auto adaptation so we need to tune the PHYs > > according to the use case (considering channel loss, etc). This is why = we >=20 > So not same? Decide. Either it is same or not, cannot be both. >=20 > If you mean that some wiring is different on the board, then how does it > differ in soc thus how it is per-soc property? If these are use-cases, > then how is even suitable for DT? >=20 > I use your Tesla FSD differently and then I exchange DTSI and compatibles= ? >=20 > You are no describing real problem and both binding and your > explanations are vague and imprecise. Binding tells nothing about it, so > it is example of skipping important decisions. >=20 > > have 2 different SW PHY initialization sequence depending on the instan= ce > > number. Do you think having different compatible (something like > > tesla,fsd-pcie-phy0 and tesla,fsd-pcie-phy1) and having phy ID as platf= orm data > > is okay in this case? I actually took reference from files like: >=20 > And in different use case on same soc you are going to reverse > compatibles or instance IDs? > Even though both the PHYs are exactly identical in terms of hardware, they need to be programmed/initialized/configured differently. Sorry for my misuse of the word =22use-case=22. To clarify, these configura= tions will always remain the same for FSD SoC even if you use it differently. I will use different compatibles for them as I understand that it is the be= st option. =20 > > drivers/usb/phy/phy-am335x-control.c >=20 > So you took 15 years old hardware, code and binding as an example. >=20 > No, don't do that ever. >=20 > Anyway, poor choices even in newer code should not drive your design. > Design it properly, describe the hardware. >=20 > > drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c > > who use alias to differentiate between register offsets for instances. >=20 >=20 >=20 > Best regards, > Krzysztof