Re: [PATCH v10 04/17] CXL/AER: Introduce CXL specific AER driver file

["Bowman, Terry" <terry.bowman@amd.com>]

On 7/23/2025 7:01 PM, dan.j.williams@intel.com wrote:
> Terry Bowman wrote:
>> The CXL AER error handling logic currently resides in the AER driver file,
>> drivers/pci/pcie/aer.c. CXL specific changes are conditionally compiled
>> using #ifdefs.
>>
>> Improve the AER driver maintainability by separating the CXL specific logic
>> from the AER driver's core functionality and removing the #ifdefs.
>> Introduce drivers/pci/pcie/cxl_aer.c and move the CXL AER logic into the
>> new file.
>>
>> Update the makefile to conditionally compile the CXL file using the
>> existing CONFIG_PCIEAER_CXL Kconfig.
>>
>> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> [..]
>> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
>> index e2d71b6fdd84..31b3935bf189 100644
>> --- a/include/linux/pci_ids.h
>> +++ b/include/linux/pci_ids.h
>> @@ -12,6 +12,8 @@
>>  
>>  /* Device classes and subclasses */
>>  
>> +#define PCI_CLASS_CODE_MASK             0xFFFF00
> Per other comments do not add this updated in the same patch as the
> move.
>
> When / if you submit it separately it likely also belongs next to
> PCI_CLASS_REVISION in include/uapi/linux/pci_regs.h defined with
> __GENMASK(23, 8).

include/uapi/linux/pci_regs.h appears to use all values without using GENMASK().
Just adding as a note. I'm making the change.

> Otherwise, with this change dropped you can add:
>
> Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Your next email pauses this. I'll respond there.

-Terry