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Wed, 06 Aug 2025 13:41:38 -0700 (PDT) Received: from [10.67.48.245] ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-241e8977896sm167085995ad.79.2025.08.06.13.41.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 06 Aug 2025 13:41:37 -0700 (PDT) Message-ID: <0a518bd3-0a20-4b69-a29f-04b5cd3c3ea8@broadcom.com> Date: Wed, 6 Aug 2025 13:41:35 -0700 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] PCI: brcmstb: Add panic/die handler to driver To: Bjorn Helgaas , Jim Quinlan Cc: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , open list References: <20250806185051.GA10150@bhelgaas> Content-Language: en-US From: Florian Fainelli Autocrypt: addr=florian.fainelli@broadcom.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 8/6/25 11:50, Bjorn Helgaas wrote: >> I'm not sure I understand the "racy" comment. If the PCIe bridge is >> off, we do not read the PCIe error registers. In this case, PCIe is >> probably not the cause of the panic. In the rare case the PCIe >> bridge is off and it was the PCIe that caused the panic, nothing >> gets reported, and this is where we are without this commit. >> Perhaps this is what you mean by "mostly-works". But this is the >> best that can be done with SW given our HW. > > Right, my fault. The error report registers don't look like standard > PCIe things, so I suppose they are on the host side, not the PCIe > side, so they're probably guaranteed to be accessible and non-racy > unless the bridge is in reset. To expand upon that part, the situation that I ran in we had the PCIe link down and therefore clock gated the PCIe root complex hardware to conserve power. Eventually I did hit a voluntary panic, and since all panic notifiers registered are invoked in succession, the one registered for the PCIe RC was invoked as well and accessing clock gated registers would not work and trigger another fault which would be confusing and mingle with the panic I was trying to debug initially. Hence this check, and a clock gated PCIe RC would not be logging any errors anyway. -- Florian