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Fri, 08 Aug 2025 04:26:56 -0700 (PDT) Message-ID: <0addc570-a3c6-4d7e-9cbd-06eedd2447bb@tuxon.dev> Date: Fri, 8 Aug 2025 14:26:54 +0300 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 4/9] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Add documentation for the PCIe IP on Renesas RZ/G3S To: Krzysztof Kozlowski , Bjorn Helgaas Cc: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, lizhi.hou@amd.com, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea , Wolfram Sang References: <20250709132449.GA2193594@bhelgaas> <2e0d815a-774a-4e31-92f1-71e0772294c7@kernel.org> From: Claudiu Beznea Content-Language: en-US In-Reply-To: <2e0d815a-774a-4e31-92f1-71e0772294c7@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi, all, Apologies for the late reply. On 09.07.2025 16:43, Krzysztof Kozlowski wrote: > On 09/07/2025 15:24, Bjorn Helgaas wrote: >> On Wed, Jul 09, 2025 at 08:47:05AM +0200, Krzysztof Kozlowski wrote: >>> On 08/07/2025 18:34, Bjorn Helgaas wrote: >>>> On Fri, Jul 04, 2025 at 07:14:04PM +0300, Claudiu wrote: >>>>> From: Claudiu Beznea >>>>> >>>>> The PCIe IP available on the Renesas RZ/G3S complies with the PCI Express >>>>> Base Specification 4.0. It is designed for root complex applications and >>>>> features a single-lane (x1) implementation. Add documentation for it. >>>> >>>>> +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml >>>> >>>> The "r9a08g045s33" in the filename seems oddly specific. Does it >>>> leave room for descendants of the current chip that will inevitably be >>>> added in the future? Most bindings are named with a fairly generic >>>> family name, e.g., "fsl,layerscape", "hisilicon,kirin", "intel, >>>> keembay", "samsung,exynos", etc. >>>> >>> >>> Bindings should be named by compatible, not in a generic way, so name is >>> correct. It can always grow with new compatibles even if name matches >>> old one, it's not a problem. >> >> Ok, thanks! >> >> I guess that means I'm casting shade on the "r9a08g045s33" compatible. >> I suppose it means something to somebody. > > Well, I hope it matches the name of the SoC, from which the compatible > should come :) The r9a08g45s33 is the part number of a device from the RZ/G3S group. This particular device from RZ/G3S group supports PCIe. In the RZ/G3S group there are more SoC variants (each with its own part number). Not all support PCIe. To differentiate b/w PCIe and non-PCIe variants it has been chosen to use the full part number here. The available RZ/G3S part numbers are listed in Table 1.1 Product Lineup at [1] (The following steps should be followed to access the manual: 1/ Click the "User Manual" button 2/ Click "Confirm"; this will start downloading an archive 3/ Open the downloaded archive 4/ Navigate to r01uh1014ej*-rzg3s-users-manual-hardware -> Deliverables 5/ Open the file r01uh1014ej*-rzg3s.pdf) We use a similar compatible scheme in other drivers. Geert, I may be wrong. Please correct me otherwise, as I don't have the full picture of this. Maybe, the other variant would be to use "renesas,rzg3s-pcie", or maybe a more generic one "renesas,rz-pcie" (though I think this last one is too generic). Geert, please let us know if you have some suggestions here with regards to the compatible. The IP on RZ/G3S is compatible also with the one in RZ/V2H, RZ/G3E. Thank you, Claudiu [1] https://www.renesas.com/en/products/rz-g3s?queryID=695cc067c2d89e3f271d43656ede4d12 > > Best regards, > Krzysztof