From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Subject: Re: [RFC 01/10] PCI: dwc: Add MSI-X callbacks handler To: Gustavo Pimentel , "bhelgaas@google.com" , "lorenzo.pieralisi@arm.com" , "Joao.Pinto@synopsys.com" , "jingoohan1@gmail.com" , "adouglas@cadence.com" , "niklas.cassel@axis.com" , "jesper.nilsson@axis.com" References: <77b7b2687e9618d3f7d1f11c3fc6ecec9a9442ef.1523379766.git.gustavo.pimentel@synopsys.com> <0b7023d9-29c6-0993-07d3-b046d25b67ff@ti.com> CC: "linux-pci@vger.kernel.org" , "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" From: Kishon Vijay Abraham I Message-ID: <0e8b8ce9-db12-1e11-3eb5-62f3fa686d59@ti.com> Date: Tue, 24 Apr 2018 12:37:58 +0530 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="windows-1252" Sender: linux-kernel-owner@vger.kernel.org List-ID: Hi, On Monday 23 April 2018 03:06 PM, Gustavo Pimentel wrote: > Hi Kishon, > > On 16/04/2018 10:29, Kishon Vijay Abraham I wrote: >> Hi Gustavo, >> >> On Tuesday 10 April 2018 10:44 PM, Gustavo Pimentel wrote: >>> Changes the pcie_raise_irq function signature, namely the interrupt_num >>> variable type from u8 to u16 to accommodate the MSI-X maximum interrupts >>> of 2048. >>> >>> Implements a PCIe config space capability iterator function to search and >>> save the MSI and MSI-X pointers. With this method the code becomes more >>> generic and flexible. >>> >>> Implements MSI-X set/get functions for sysfs interface in order to change >>> the EP entries number. >>> >>> Implements EP MSI-X interface for triggering interruptions. >>> >>> Signed-off-by: Gustavo Pimentel >>> --- >>> drivers/pci/dwc/pci-dra7xx.c | 2 +- >>> drivers/pci/dwc/pcie-artpec6.c | 2 +- >>> drivers/pci/dwc/pcie-designware-ep.c | 145 ++++++++++++++++++++++++++++++++- >>> drivers/pci/dwc/pcie-designware-plat.c | 6 +- >>> drivers/pci/dwc/pcie-designware.h | 23 +++++- >>> 5 files changed, 173 insertions(+), 5 deletions(-) >>> >>> diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c >>> index ed8558d..5265725 100644 >>> --- a/drivers/pci/dwc/pci-dra7xx.c >>> +++ b/drivers/pci/dwc/pci-dra7xx.c >>> @@ -369,7 +369,7 @@ static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx, >>> } >>> >>> static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, >>> - enum pci_epc_irq_type type, u8 interrupt_num) >>> + enum pci_epc_irq_type type, u16 interrupt_num) >>> { >>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep); >>> struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); >>> diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c >>> index e66cede..96dc259 100644 >>> --- a/drivers/pci/dwc/pcie-artpec6.c >>> +++ b/drivers/pci/dwc/pcie-artpec6.c >>> @@ -428,7 +428,7 @@ static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep) >>> } >>> >>> static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, >>> - enum pci_epc_irq_type type, u8 interrupt_num) >>> + enum pci_epc_irq_type type, u16 interrupt_num) >>> { >>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep); >>> >>> diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c >>> index 15b22a6..874d4c2 100644 >>> --- a/drivers/pci/dwc/pcie-designware-ep.c >>> +++ b/drivers/pci/dwc/pcie-designware-ep.c >>> @@ -40,6 +40,44 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) >>> __dw_pcie_ep_reset_bar(pci, bar, 0); >>> } >>> >>> +void dw_pcie_ep_find_cap_addr(struct dw_pcie_ep *ep) >>> +{ >> >> This should be implemented in a generic way similar to pci_find_capability(). >> It'll be useful when we try to implement other capabilities as well. > > Hum, what you suggest? Something implemented on the pci-epf-core? yeah, Initially thought it could be implemented as a helper function in pci-epc-core so that both designware and cadence can use it. But do we really have to find the address like this? since all designware IP's will have a particular capability at a fixed address offset, why not follow use existing mechanism in dw_pcie_ep_get_msi? Or is it possible for a particular capability to have address offsets for different vendors? How is it for cadence? Thanks Kishon