From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: Vidya Sagar <vidyas@nvidia.com>, <thierry.reding@gmail.com>,
<bhelgaas@google.com>, <jonathanh@nvidia.com>
Cc: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<kthota@nvidia.com>
Subject: Re: [PATCH 04/12] PCI: tegra: Advertise AER capability
Date: Mon, 30 Oct 2017 09:24:15 +0530 [thread overview]
Message-ID: <10a9ba6c-7a4d-6eab-2c8c-dbd86de67727@nvidia.com> (raw)
In-Reply-To: <64d00808-9c79-86b5-130d-835e3e5d5c1c@nvidia.com>
On 29-Oct-17 3:09 PM, Vidya Sagar wrote:
>
>
> On Saturday 28 October 2017 12:59 AM, Manikanta Maddireddy wrote:
>> Default root port settings hide AER capability. This patch enables the
>> advertisement of AER capability by root port.
>>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>> drivers/pci/host/pci-tegra.c | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
>> index 15df60e13a14..c0cd88103e9e 100644
>> --- a/drivers/pci/host/pci-tegra.c
>> +++ b/drivers/pci/host/pci-tegra.c
>> @@ -187,6 +187,9 @@
>> #define RP_VEND_XP 0x00000f00
>> #define RP_VEND_XP_DL_UP (1 << 30)
>> +#define RP_VEND_CTL1 0xf48
>> +#define RP_VEND_CTL1_ERPT (1 << 13)
> BIT macro is preferred here.
Left shift is used everywhere, so to be inline with that I used same format
>> +
>> #define RP_VEND_CTL2 0x00000fa8
>> #define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
>> @@ -2055,6 +2058,16 @@ static void tegra_pcie_apply_pad_settings(struct tegra_pcie *pcie)
>> pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
>> }
>> +static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
>> +{
>> + unsigned long value;
>> +
>> + /* Enable AER capability */
>> + value = readl(port->base + RP_VEND_CTL1);
>> + value |= RP_VEND_CTL1_ERPT;
>> + writel(value, port->base + RP_VEND_CTL1);
>> +}
>> +
>> /*
>> * FIXME: If there are no PCIe cards attached, then calling this function
>> * can result in the increase of the bootup time as there are big timeout
>> @@ -2119,6 +2132,7 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
>> port->index, port->lanes);
>> tegra_pcie_port_enable(port);
>> + tegra_pcie_enable_rp_features(port);
>> }
>> /* take the PCIe interface module out of reset */
>
next prev parent reply other threads:[~2017-10-30 3:55 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-27 19:29 [PATCH 00/12] Enable Tegra root port features and apply SW fixups Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 01/12] PCI: tegra: Start LTSSM after programming root port Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 02/12] PCI: tegra: Move REFCLK pad settings out of phy_power_on() Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 03/12] PCI: tegra: Retrain link for Gen2 speed Manikanta Maddireddy
2017-10-29 9:34 ` Vidya Sagar
2017-10-29 9:38 ` Vidya Sagar
2017-10-30 3:51 ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 04/12] PCI: tegra: Advertise AER capability Manikanta Maddireddy
2017-10-29 9:39 ` Vidya Sagar
2017-10-30 3:54 ` Manikanta Maddireddy [this message]
2017-10-27 19:29 ` [PATCH 05/12] PCI: tegra: Program UPHY electrical settings in Tegra210 Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 06/12] PCI: tegra: Enable opportunistic update FC and ACK Manikanta Maddireddy
2017-10-29 9:41 ` Vidya Sagar
2017-10-30 3:55 ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 07/12] PCI: tegra: Disable AFI dynamic clock gating Manikanta Maddireddy
2017-10-29 9:42 ` Vidya Sagar
2017-10-30 3:55 ` Manikanta Maddireddy
2017-10-30 15:58 ` David Laight
2017-10-30 16:18 ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 08/12] PCI: tegra: Wait for DLLP to finish before entering L1 or L2 Manikanta Maddireddy
2017-10-29 9:42 ` Vidya Sagar
2017-10-30 3:56 ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 09/12] PCI: tegra: Enable PCIe xclk clock clamping Manikanta Maddireddy
2017-10-29 9:43 ` Vidya Sagar
2017-10-30 3:56 ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 10/12] PCI: tegra: Add SW fixup for RAW violations Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 11/12] PCI: tegra: Increase the deskew retry time Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 12/12] PCI: tegra: Update flow control threshold in Tegra210 Manikanta Maddireddy
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=10a9ba6c-7a4d-6eab-2c8c-dbd86de67727@nvidia.com \
--to=mmaddireddy@nvidia.com \
--cc=bhelgaas@google.com \
--cc=jonathanh@nvidia.com \
--cc=kthota@nvidia.com \
--cc=linux-pci@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=thierry.reding@gmail.com \
--cc=vidyas@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).