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Fri, 18 Apr 2025 20:24:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHaTLsO8K9DHo37Za0IPN5HYN8SJIK2QtZbWVmGymla/Zh5qrFN4liImOueE+bM2dukZ9s+aQ== X-Received: by 2002:a05:6a00:3d02:b0:736:4e0a:7e82 with SMTP id d2e1a72fcca58-73dc1480119mr5697337b3a.10.1745033076682; Fri, 18 Apr 2025 20:24:36 -0700 (PDT) Received: from [192.168.29.92] ([49.43.228.124]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73dbf8c0857sm2463609b3a.16.2025.04.18.20.24.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Apr 2025 20:24:36 -0700 (PDT) Message-ID: <115bcef9-c35c-6a80-e0a6-c862e6b6f011@oss.qualcomm.com> Date: Sat, 19 Apr 2025 08:54:26 +0530 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v5 8/9] PCI: pwrctrl: Add power control driver for tc9563 Content-Language: en-US To: Bjorn Helgaas Cc: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , chaitanya chundru , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org, Jingoo Han , Bartosz Golaszewski , quic_vbadigan@quicnic.com, amitk@kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jorge.ramirez@oss.qualcomm.com, Dmitry Baryshkov , Bartosz Golaszewski References: <20250418201631.GA82526@bhelgaas> From: Krishna Chaitanya Chundru In-Reply-To: <20250418201631.GA82526@bhelgaas> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: Cr8F5FK9N-_CaS7i3_qnJlMbHs5OD2FE X-Proofpoint-GUID: Cr8F5FK9N-_CaS7i3_qnJlMbHs5OD2FE X-Authority-Analysis: v=2.4 cv=ANaQCy7k c=1 sm=1 tr=0 ts=68031776 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=M6NtEvFuFW5htA+UmNA0rQ==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=gmMK7q8T0ENcM4QI6agA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-19_01,2025-04-17_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 mlxlogscore=999 suspectscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 impostorscore=0 spamscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504190025 On 4/19/2025 1:46 AM, Bjorn Helgaas wrote: > On Sat, Apr 12, 2025 at 07:19:57AM +0530, Krishna Chaitanya Chundru wrote: >> TC9563 is a PCIe switch which has one upstream and three downstream >> ports. To one of the downstream ports ethernet MAC is connected as endpoint >> device. Other two downstream ports are supposed to connect to external >> device. One Host can connect to TC9563 by upstream port. TC9563 switch >> needs to be configured after powering on and before PCIe link was up. > > This is described as a generic driver for TC9563, but the ethernet MAC > stuff built into doesn't sound generic. Maybe this could be clarified > here and in the Kconfig help text. > The switch has a DSP to which embedded ethernet was connected, I will update the text in next patch. >> +#define TC9563_GPIO_CONFIG 0x801208 >> +#define TC9563_RESET_GPIO 0x801210 > > I guess these are i2c register addresses? > yes >> +#define TC9563_BUS_CONTROL 0x801014 > > Unused. > I will remove >> +#define TC9563_PORT_L0S_DELAY 0x82496c >> +#define TC9563_PORT_L1_DELAY 0x824970 > > I guess these correspond to "L0s Exit Latency" and "L1 Exit Latency" > in the PCIe spec? Can we name them to suggest that? Where do the > values come from? > ack >> +#define TC9563_EMBEDDED_ETH_DELAY 0x8200d8 >> +#define TC9563_ETH_L1_DELAY_MASK GENMASK(27, 18) >> +#define TC9563_ETH_L1_DELAY_VALUE(x) FIELD_PREP(TC9563_ETH_L1_DELAY_MASK, x) >> +#define TC9563_ETH_L0S_DELAY_MASK GENMASK(17, 13) >> +#define TC9563_ETH_L0S_DELAY_VALUE(x) FIELD_PREP(TC9563_ETH_L0S_DELAY_MASK, x) > >> +#define TC9563_PWRCTL_MAX_SUPPLY 6 >> + >> +struct tc9563_pwrctrl_ctx { >> + struct regulator_bulk_data supplies[TC9563_PWRCTL_MAX_SUPPLY]; >> + struct tc9563_pwrctrl_cfg cfg[TC9563_MAX]; >> + struct gpio_desc *reset_gpio; >> + struct i2c_adapter *adapter; >> + struct i2c_client *client; >> + struct pci_pwrctrl pwrctrl; >> +}; > >> +static int tc9563_pwrctrl_i2c_write(struct i2c_client *client, >> + u32 reg_addr, u32 reg_val) >> +{ >> + struct i2c_msg msg; >> + u8 msg_buf[7]; >> + int ret; >> + >> + msg.addr = client->addr; >> + msg.len = 7; >> + msg.flags = 0; >> + >> + /* Big Endian for reg addr */ >> + put_unaligned_be24(reg_addr, &msg_buf[0]); > > Of the 1000+ calls to i2c_transfer(), I only see about 25 uses of > put_unaligned_be*() beforehand. Are most of the other 975 calls > broken? Or maybe they are only used on platforms of known endianness > so they don't need it? Just a question; I have no idea how i2c works. > The I2C in the switch expects big endian format for address and this requirement is specific to i2c on this switch only. Not every i2c devices may have this requirement. >> + /* Little Endian for reg val */ >> + put_unaligned_le32(reg_val, &msg_buf[3]); >> + >> + msg.buf = msg_buf; >> + ret = i2c_transfer(client->adapter, &msg, 1); >> + return ret == 1 ? 0 : ret; >> +} > >> + ret = of_property_read_u8_array(node, "nfts", cfg->nfts, 2); >> + if (ret && ret != -EINVAL) >> + return ret; > > Asked elsewhere whether "nfts" is supposed to match the DT "n-fts" > property. > ack it is a miss from my side, I will fix in next patch. Thanks for catching this. >> +static int tc9563_pwrctrl_bring_up(struct tc9563_pwrctrl_ctx *ctx) >> +{ >> + struct tc9563_pwrctrl_cfg *cfg; >> + int ret, i; >> + >> + ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); >> + if (ret < 0) >> + return dev_err_probe(ctx->pwrctrl.dev, ret, "cannot enable regulators\n"); >> + >> + gpiod_set_value(ctx->reset_gpio, 0); >> + >> + /* wait for the internal osc frequency to stablise */ > > s/stablise/stabilize/ (or "stabilise" if you prefer) > >> + usleep_range(10000, 10500); > > Where do these values come from? Can we add a spec citation? > This is from The tc9653 databook. I will add spec citation in next patch. >> + ret = tc9563_pwrctrl_set_l0s_l1_entry_delay(ctx, i, false, cfg->l0s_delay); >> + if (ret) { >> + dev_err(ctx->pwrctrl.dev, "Setting L0s entry delay failed\n"); > > Since these are *entry* delays, maybe they're not related to the "Exit > Latencies" from the PCIe spec. But if they *are* related, can we use > the same terms here? > These are entry delays, not the exit latencies from the Spec. >> + ret = tc9563_pwrctrl_set_l0s_l1_entry_delay(ctx, i, true, cfg->l1_delay); >> + if (ret) { >> + dev_err(ctx->pwrctrl.dev, "Setting L1 entry delay failed\n"); > >> + ret = tc9563_pwrctrl_set_tx_amplitude(ctx, i, cfg->tx_amp); >> + if (ret) { >> + dev_err(ctx->pwrctrl.dev, "Setting Tx amplitube failed\n"); > > s/amplitube/amplitude/ > >> + goto power_off; >> + } >> + >> + ret = tc9563_pwrctrl_set_nfts(ctx, i, cfg->nfts); >> + if (ret) { >> + dev_err(ctx->pwrctrl.dev, "Setting nfts failed\n"); > > s/nfts/N_FTS/ to match spec usage. > >> +static int tc9563_pwrctrl_probe(struct platform_device *pdev) >> +{ > >> ... >> + ctx->supplies[0].supply = "vddc"; >> + ctx->supplies[1].supply = "vdd18"; >> + ctx->supplies[2].supply = "vdd09"; >> + ctx->supplies[3].supply = "vddio1"; >> + ctx->supplies[4].supply = "vddio2"; >> + ctx->supplies[5].supply = "vddio18"; > > Seems like this could be made into a const static array, maybe next to > TC9563_PWRCTL_MAX_SUPPLY? > ack >> + for_each_child_of_node_scoped(pdev->dev.of_node, child) { >> + ret = tc9563_pwrctrl_parse_device_dt(ctx, child, port++); >> + if (ret) >> + break; >> + /* Embedded ethernet device are under DSP3 */ >> + if (port == TC9563_DSP3) > > Is this ethernet thing integrated into the TC9563? Seems like the > sort of topology thing that would normally be described via DT. > The switch has inbuilt integrated ethernet and we described in the DT for the same. - Krishna Chaitanya. >> + for_each_child_of_node_scoped(child, child1) { >> + ret = tc9563_pwrctrl_parse_device_dt(ctx, child1, port++); >> + if (ret) >> + break; >> + } >> + } > > Bjorn