From: Yinghai Lu <yinghai@kernel.org>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Ram Pai <linuxram@us.ibm.com>,
Linus Torvalds <torvalds@linux-foundation.org>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
Yinghai Lu <yinghai@kernel.org>
Subject: [PATCH 17/21] PCI: Disable cardbus bridge MEM1 pref CTL
Date: Sat, 21 Jan 2012 02:08:33 -0800 [thread overview]
Message-ID: <1327140517-14811-18-git-send-email-yinghai@kernel.org> (raw)
In-Reply-To: <1327140517-14811-1-git-send-email-yinghai@kernel.org>
Some BIOS enable both pref for MEM0 and MEM1.
but we assume MEM1 is non-pref...
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
---
drivers/pci/setup-bus.c | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 090217a..d5897c3 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -914,6 +914,14 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
if (realloc_head)
add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, 0 /* dont care */);
+ /* MEM1 must not be pref mmio */
+ pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
+ if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
+ ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
+ pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
+ pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
+ }
+
/*
* Check whether prefetchable memory is supported
* by this bridge.
--
1.7.7
next prev parent reply other threads:[~2012-01-21 10:09 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-01-21 10:08 [PATCH 00/21] PCI : bridge resource reallocation patchset Yinghai Lu
2012-01-21 10:08 ` [PATCH 01/21] PCI : Calculate right add_size Yinghai Lu
2012-01-27 17:55 ` Jesse Barnes
2012-01-21 10:08 ` [PATCH 02/21] PCI: Make add_to_list() return status Yinghai Lu
2012-01-21 10:08 ` [PATCH 03/21] PCI: Move get_res_add_size() early Yinghai Lu
2012-01-21 10:08 ` [PATCH 04/21] PCI: Try to assign required+option size at first Yinghai Lu
2012-01-21 10:08 ` [PATCH 05/21] PCI: Using add_list in pcie hotplug path Yinghai Lu
2012-01-21 10:08 ` [PATCH 06/21] PCI: Make rescan bus could increase bridge resource size if needed Yinghai Lu
2012-01-27 18:00 ` Jesse Barnes
2012-01-21 10:08 ` [PATCH 07/21] PCI: Make pci_rescan_bus handle add_list Yinghai Lu
2012-01-21 10:08 ` [PATCH 08/21] PCI: Fixing multiple retrying with pci resource optional resources allocation under multi bridges Yinghai Lu
2012-01-21 10:08 ` [PATCH 09/21] PCI: Move pdev_sort_resources() to setup-bus.c Yinghai Lu
2012-01-21 10:08 ` [PATCH 10/21] PCI: Move struct resource_list " Yinghai Lu
2012-01-21 10:08 ` [PATCH 11/21] PCI: Replace resource_list with generic list Yinghai Lu
2012-01-21 10:08 ` [PATCH 12/21] PCI: Merge pci_dev_resource_x and pci_dev_resource Yinghai Lu
2012-01-21 10:08 ` [PATCH 13/21] PCI: Rename dev_res_x to add_res or fail_res Yinghai Lu
2012-01-21 10:08 ` [PATCH 14/21] PCI: Change free_list() to function Yinghai Lu
2012-01-21 10:08 ` [PATCH 15/21] PCI: add debug print out for add_size Yinghai Lu
2012-01-21 10:08 ` [PATCH 16/21] PCI: remove add_to_failed_list() Yinghai Lu
2012-01-27 18:21 ` Jesse Barnes
2012-01-21 10:08 ` Yinghai Lu [this message]
2012-01-27 18:22 ` [PATCH 17/21] PCI: Disable cardbus bridge MEM1 pref CTL Jesse Barnes
2012-01-27 18:39 ` Yinghai Lu
2012-01-21 10:08 ` [PATCH 18/21] PCI: Fix cardbus bridge resources as optional size handling Yinghai Lu
2012-01-27 18:23 ` Jesse Barnes
2012-01-27 21:37 ` Yinghai Lu
2012-02-05 21:58 ` Dominik Brodowski
2012-02-05 23:30 ` Yinghai Lu
2012-02-10 15:35 ` Dominik Brodowski
2012-02-10 17:07 ` Yinghai Lu
2012-01-21 10:08 ` [PATCH 19/21] PCI: Retry on type IORESOURCE_IO allocation Yinghai Lu
2012-01-21 10:08 ` [PATCH 20/21] PCI: Make pci bridge reallocating enabled/disabled Yinghai Lu
2012-01-21 10:08 ` [PATCH 21/21] PCI: only enable pci realloc when SRIOV bar is not assigned Yinghai Lu
2012-01-27 18:25 ` Jesse Barnes
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