From: Nikhil P Rao <nikhil.rao@intel.com>
To: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
Jesse Barnes <jbarnes@virtuousgeek.org>
Subject: Re: [PATCH] pci: support alignments upto 8Gb in pbus_size_mem()
Date: Mon, 25 Jun 2012 13:54:47 -0700 [thread overview]
Message-ID: <1340657687.36341.178.camel@localhost.localdomain> (raw)
In-Reply-To: <CAErSpo7AWQCofnTRhtMKVP3pm_BDq9v+axGpide0RbmignsV9A@mail.gmail.com>
On Sat, 2012-06-23 at 12:15 -0600, Bjorn Helgaas wrote:
> On Thu, Jun 21, 2012 at 5:47 PM, Nikhil P Rao <nikhil.rao@intel.com> wrote:
> > I ran into the "disabling BAR .." error message when
> > trying to use a 8Gb PCIe card on a system with a BIOS
> > that didnt have support for BAR size > 2Gb.
>
> So the BIOS left the 8Gb BAR unassigned, and you got the "disabling
> BAR ... (bad alignment)" message when Linux tried to enable it?
Yes.
> How do we know 8Gb is the correct new limit? Are we going to be
> fixing this again when we see a 16Gb or a 32Gb BAR? Do we need a
> better algorithm that doesn't have a limit like this?
>
The original error message seems applicable to 32bit archs. and not to
64 bit archs. How about the patch below - is aligns[44] (256bytes more)
acceptable ?
From: Nikhil P Rao <nikhil.rao@intel.com>
Date: Mon, 25 Jun 2012 13:33:55 -0700
Subject: [PATCH] pci: fix resource size check
Support a PCI BAR alignment of > 2Gb, the original check was
only applicable to 32 bit kernels,
Signed-off-by: Nikhil P Rao <nikhil.rao@intel.com>
---
drivers/pci/setup-bus.c | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 8fa2d4b..9f8d9ea 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -780,7 +780,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
{
struct pci_dev *dev;
resource_size_t min_align, align, size, size0, size1;
- resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
+ resource_size_t aligns[44]; /* Alignments from 1Mb to 2^63 */
int order, max_order;
struct resource *b_res = find_free_bus_resource(bus, type);
unsigned int mem64_mask = 0;
@@ -819,7 +819,8 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
/* For bridges size != alignment */
align = pci_resource_alignment(dev, r);
order = __ffs(align) - 20;
- if (order > 11) {
+ if ((sizeof(size_t) == 4 && order > 11) ||
+ (sizeof(size_t) == 8 && order > 43)) {
dev_warn(&dev->dev, "disabling BAR %d: %pR "
"(bad alignment %#llx)\n", i, r,
(unsigned long long) align);
--
1.7.1
next prev parent reply other threads:[~2012-06-25 20:54 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-20 19:56 [PATCH] pci: 64bit resource fix in setup-res.c Nikhil P Rao
2012-06-21 23:47 ` [PATCH] pci: support alignments upto 8Gb in pbus_size_mem() Nikhil P Rao
2012-06-23 18:15 ` Bjorn Helgaas
2012-06-25 20:54 ` Nikhil P Rao [this message]
2012-07-11 22:53 ` Bjorn Helgaas
2012-07-12 0:13 ` Yinghai Lu
2012-07-12 20:34 ` Bjorn Helgaas
2012-07-11 23:12 ` [PATCH] pci: 64bit resource fix in setup-res.c Bjorn Helgaas
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