[PATCH 01/12] PCI: Add and use standard PCI-X Capability register names

[PATCH 01/12] PCI: Add and use standard PCI-X Capability register names

[Bjorn Helgaas]

Add and use #defines for PCI-X Capability registers and fields.
Note that the PCI-X Capability has a different layout for
type 0 (endpoint) and type 1 (bridge) devices.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Matthew Wilcox <willy@linux.intel.com>
---
 drivers/pci/probe.c           |   15 +++++++++------
 include/uapi/linux/pci_regs.h |   15 ++++++++++++++-
 2 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index ec909af..81d0667 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -579,14 +579,16 @@ static void pci_set_bus_speed(struct pci_bus *bus)
 	if (pos) {
 		u16 status;
 		enum pci_bus_speed max;
-		pci_read_config_word(bridge, pos + 2, &status);
 
-		if (status & 0x8000) {
+		pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
+				     &status);
+
+		if (status & PCI_X_SSTATUS_533MHZ) {
 			max = PCI_SPEED_133MHz_PCIX_533;
-		} else if (status & 0x4000) {
+		} else if (status & PCI_X_SSTATUS_266MHZ) {
 			max = PCI_SPEED_133MHz_PCIX_266;
-		} else if (status & 0x0002) {
-			if (((status >> 12) & 0x3) == 2) {
+		} else if (status & PCI_X_SSTATUS_133MHZ) {
+			if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) {
 				max = PCI_SPEED_133MHz_PCIX_ECC;
 			} else {
 				max = PCI_SPEED_133MHz_PCIX;
@@ -596,7 +598,8 @@ static void pci_set_bus_speed(struct pci_bus *bus)
 		}
 
 		bus->max_bus_speed = max;
-		bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
+		bus->cur_bus_speed = pcix_bus_speed[
+			(status & PCI_X_SSTATUS_FREQ) >> 6];
 
 		return;
 	}
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 20ae747..4cca834 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -349,7 +349,7 @@
 #define  PCI_AF_STATUS_TP	0x01
 #define PCI_CAP_AF_SIZEOF	6	/* size of AF registers */
 
-/* PCI-X registers */
+/* PCI-X registers (Type 0 (non-bridge) devices) */
 
 #define PCI_X_CMD		2	/* Modes & Features */
 #define  PCI_X_CMD_DPERR_E	0x0001	/* Data Parity Error Recovery Enable */
@@ -389,6 +389,19 @@
 #define PCI_CAP_PCIX_SIZEOF_V1	24	/* size for Version 1 */
 #define PCI_CAP_PCIX_SIZEOF_V2	PCI_CAP_PCIX_SIZEOF_V1	/* Same for v2 */
 
+/* PCI-X registers (Type 1 (bridge) devices) */
+
+#define PCI_X_BRIDGE_SSTATUS	2	/* Secondary Status */
+#define  PCI_X_SSTATUS_64BIT	0x0001	/* Secondary AD interface is 64 bits */
+#define  PCI_X_SSTATUS_133MHZ	0x0002	/* 133 MHz capable */
+#define  PCI_X_SSTATUS_FREQ	0x03c0	/* Secondary Bus Mode and Frequency */
+#define  PCI_X_SSTATUS_VERS	0x3000	/* PCI-X Capability Version */
+#define  PCI_X_SSTATUS_V1	0x1000	/* Mode 2, not Mode 1 */
+#define  PCI_X_SSTATUS_V2	0x2000	/* Mode 1 or Modes 1 and 2 */
+#define  PCI_X_SSTATUS_266MHZ	0x4000	/* 266 MHz capable */
+#define  PCI_X_SSTATUS_533MHZ	0x8000	/* 533 MHz capable */
+#define PCI_X_BRIDGE_STATUS	4	/* Bridge Status */
+
 /* PCI Bridge Subsystem ID registers */
 
 #define PCI_SSVID_VENDOR_ID     4	/* PCI-Bridge subsystem vendor id register */

[PATCH 02/12] PCI: Use standard PCIe Capability Link register field names

[Bjorn Helgaas]

Use the standard #defines for PCIe Link Status and Capability registers
rather than bare numbers.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
 drivers/pci/probe.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 81d0667..7ec6973 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -521,7 +521,7 @@ static unsigned char pcie_link_speed[] = {
 
 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
 {
-	bus->cur_bus_speed = pcie_link_speed[linksta & 0xf];
+	bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
 }
 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
 
@@ -610,7 +610,7 @@ static void pci_set_bus_speed(struct pci_bus *bus)
 		u16 linksta;
 
 		pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
-		bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
+		bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
 
 		pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
 		pcie_update_link_speed(bus, linksta);

[PATCH 03/12] PCI/portdrv: Use PCI Express Capability accessors

[Bjorn Helgaas]

Use PCI Express Capability access functions to simplify portdrv.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Jiang Liu <jiang.liu@huawei.com>
---
 drivers/pci/pcie/portdrv_core.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index d03a7a3..70d3555 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -120,8 +120,7 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
 		 * the value in this field indicates which MSI-X Table entry is
 		 * used to generate the interrupt message."
 		 */
-		pos = pci_pcie_cap(dev);
-		pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &reg16);
+		pcie_capability_read_word(dev, PCI_EXP_FLAGS, &reg16);
 		entry = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9;
 		if (entry >= nr_entries)
 			goto Error;

[PATCH 04/12] [SCSI] qla2xxx: Use standard PCIe Capability Link register field names

[Bjorn Helgaas]

Use the standard #defines for PCIe Link Capability register fields
rather than bare numbers.  This also uses the new PCI Express Capability
accessor rather than reading the capability directly.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Andrew Vasquez <andrew.vasquez@qlogic.com>
CC: linux-driver@qlogic.com
CC: "James E.J. Bottomley" <JBottomley@parallels.com>
CC: linux-scsi@vger.kernel.org
---
 drivers/scsi/qla2xxx/qla_os.c |   14 +++++---------
 1 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c
index d501bf5..b5d070f 100644
--- a/drivers/scsi/qla2xxx/qla_os.c
+++ b/drivers/scsi/qla2xxx/qla_os.c
@@ -480,18 +480,14 @@ qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
 	static char *pci_bus_modes[] = { "33", "66", "100", "133", };
 	struct qla_hw_data *ha = vha->hw;
 	uint32_t pci_bus;
-	int pcie_reg;
 
-	pcie_reg = pci_pcie_cap(ha->pdev);
-	if (pcie_reg) {
+	if (pci_is_pcie(ha->pdev)) {
 		char lwstr[6];
-		uint16_t pcie_lstat, lspeed, lwidth;
+		uint32_t lstat, lspeed, lwidth;
 
-		pcie_reg += PCI_EXP_LNKCAP;
-		pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
-		lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
-		lwidth = (pcie_lstat &
-		    (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
+		pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
+		lspeed = lstat & PCI_EXP_LNKCAP_SLS;
+		lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
 
 		strcpy(str, "PCIe (");
 		if (lspeed == 1)

[PATCH 05/12] PCI: Add standard PCIe Capability Link ASPM field names

[Bjorn Helgaas]

Add standard #defines for ASPM fields in PCI Express Link Capability and
Link Control registers.

Previously we used PCIE_LINK_STATE_L0S and PCIE_LINK_STATE_L1 directly, but
these are defined for the Linux ASPM interfaces, e.g.,
pci_disable_link_state(), and only coincidentally match the actual register
bits.  PCIE_LINK_STATE_CLKPM, also part of that interface, does not match
the register bit.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
CC: Shaohua Li <shaohua.li@intel.com>
---
 drivers/pci/pcie/aspm.c       |   11 ++++++-----
 include/uapi/linux/pci_regs.h |    2 ++
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 213753b..c2faf9d 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -427,7 +427,8 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 
 static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
 {
-	pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, 0x3, val);
+	pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
+					   PCI_EXP_LNKCTL_ASPMC, val);
 }
 
 static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
@@ -442,12 +443,12 @@ static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
 		return;
 	/* Convert ASPM state to upstream/downstream ASPM register state */
 	if (state & ASPM_STATE_L0S_UP)
-		dwstream |= PCIE_LINK_STATE_L0S;
+		dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
 	if (state & ASPM_STATE_L0S_DW)
-		upstream |= PCIE_LINK_STATE_L0S;
+		upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
 	if (state & ASPM_STATE_L1) {
-		upstream |= PCIE_LINK_STATE_L1;
-		dwstream |= PCIE_LINK_STATE_L1;
+		upstream |= PCI_EXP_LNKCTL_ASPM_L1;
+		dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
 	}
 	/*
 	 * Spec 2.0 suggests all functions should be configured the
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 4cca834..0b6dbe4 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -469,6 +469,8 @@
 #define  PCI_EXP_LNKCAP_PN	0xff000000 /* Port Number */
 #define PCI_EXP_LNKCTL		16	/* Link Control */
 #define  PCI_EXP_LNKCTL_ASPMC	0x0003	/* ASPM Control */
+#define  PCI_EXP_LNKCTL_ASPM_L0S  0x01	/* L0s Enable */
+#define  PCI_EXP_LNKCTL_ASPM_L1   0x02	/* L1 Enable */
 #define  PCI_EXP_LNKCTL_RCB	0x0008	/* Read Completion Boundary */
 #define  PCI_EXP_LNKCTL_LD	0x0010	/* Link Disable */
 #define  PCI_EXP_LNKCTL_RL	0x0020	/* Retrain Link */

[PATCH 06/12] cxgb3: Use standard #defines for PCIe Capability ASPM fields

[Bjorn Helgaas]

Use the standard #defines rather than bare numbers for PCIe Capability
ASPM fields.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Divy Le Ray <divy@chelsio.com>
CC: netdev@vger.kernel.org
---
 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
index aef45d3..3dee686 100644
--- a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
@@ -3307,7 +3307,7 @@ static void config_pcie(struct adapter *adap)
 	    G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE));
 	log2_width = fls(adap->params.pci.width) - 1;
 	acklat = ack_lat[log2_width][pldsize];
-	if (val & 1)		/* check LOsEnable */
+	if (val & PCI_EXP_LNKCTL_ASPM_L0S)	/* check LOsEnable */
 		acklat += fst_trn_tx * 4;
 	rpllmt = rpl_tmr[log2_width][pldsize] + fst_trn_rx * 4;
 

[PATCH 07/12] e1000e: Use standard #defines for PCIe Capability ASPM fields

[Bjorn Helgaas]

Use the standard #defines for PCIe Capability ASPM fields.

Previously we used PCIE_LINK_STATE_L0S and PCIE_LINK_STATE_L1 directly, but
these are defined for the Linux ASPM interfaces, e.g.,
pci_disable_link_state(), and only coincidentally match the actual register
bits.  PCIE_LINK_STATE_CLKPM, also part of that interface, does not match
the register bit.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
CC: Jesse Brandeburg <jesse.brandeburg@intel.com>
CC: Bruce Allan <bruce.w.allan@intel.com>
CC: Carolyn Wyborny <carolyn.wyborny@intel.com>
CC: Don Skidmore <donald.c.skidmore@intel.com>
CC: Greg Rose <gregory.v.rose@intel.com>
CC: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>
CC: Alex Duyck <alexander.h.duyck@intel.com>
CC: John Ronciak <john.ronciak@intel.com>
CC: e1000-devel@lists.sourceforge.net
---
 drivers/net/ethernet/intel/e1000e/netdev.c |   11 +++++++++--
 1 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
index f444eb0..b8561ef 100644
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
@@ -5613,15 +5613,22 @@ static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
 #else
 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
 {
+	u16 aspm_ctl = 0;
+
+	if (state & PCIE_LINK_STATE_L0S)
+		aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L0S;
+	if (state & PCIE_LINK_STATE_L1)
+		aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L1;
+
 	/*
 	 * Both device and parent should have the same ASPM setting.
 	 * Disable ASPM in downstream component first and then upstream.
 	 */
-	pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, state);
+	pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_ctl);
 
 	if (pdev->bus->self)
 		pcie_capability_clear_word(pdev->bus->self, PCI_EXP_LNKCTL,
-					   state);
+					   aspm_ctl);
 }
 #endif
 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)

[PATCH 08/12] ath9k: Use standard #defines for PCIe Capability ASPM fields

[Bjorn Helgaas]

Use the standard #defines for PCIe Capability ASPM fields.

Previously we used PCIE_LINK_STATE_L0S and PCIE_LINK_STATE_L1 directly, but
these are defined for the Linux ASPM interfaces, e.g.,
pci_disable_link_state(), and only coincidentally match the actual register
bits.  PCIE_LINK_STATE_CLKPM, also part of that interface, does not match
the register bit.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: "John W. Linville" <linville@tuxdriver.com>
CC: "Luis R. Rodriguez" <mcgrof@qca.qualcomm.com>
CC: Jouni Malinen <jouni@qca.qualcomm.com>
CC: Vasanthakumar Thiagarajan <vthiagar@qca.qualcomm.com>
CC: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
CC: linux-wireless@vger.kernel.org
CC: ath9k-devel@lists.ath9k.org
---
 drivers/net/wireless/ath/ath9k/pci.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index f088f4b..71d8207 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -125,23 +125,23 @@ static void ath_pci_aspm_init(struct ath_common *common)
 
 	if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) &&
 	    (AR_SREV_9285(ah))) {
-		/* Bluetooth coexistance requires disabling ASPM. */
+		/* Bluetooth coexistence requires disabling ASPM. */
 		pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
-			PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
+			PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);
 
 		/*
 		 * Both upstream and downstream PCIe components should
 		 * have the same ASPM settings.
 		 */
 		pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
-			PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
+			PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);
 
 		ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");
 		return;
 	}
 
 	pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);
-	if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
+	if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1)) {
 		ah->aspm_enabled = true;
 		/* Initialize PCIe PM and SERDES registers. */
 		ath9k_hw_configpcipowersave(ah, false);

[PATCH 09/12] iwlegacy: collapse wrapper for pcie_capability_read_word()

[Bjorn Helgaas]

il_pcie_link_ctl() has only one call site and no longer provides any useful
abstraction, so collapse it into the caller.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: "John W. Linville" <linville@tuxdriver.com>
CC: Stanislaw Gruszka <sgruszka@redhat.com>
CC: linux-wireless@vger.kernel.org
---
 drivers/net/wireless/iwlegacy/common.c |    5 +++--
 drivers/net/wireless/iwlegacy/common.h |    8 --------
 2 files changed, 3 insertions(+), 10 deletions(-)

diff --git a/drivers/net/wireless/iwlegacy/common.c b/drivers/net/wireless/iwlegacy/common.c
index 318ed3c..1811507 100644
--- a/drivers/net/wireless/iwlegacy/common.c
+++ b/drivers/net/wireless/iwlegacy/common.c
@@ -1183,8 +1183,9 @@ EXPORT_SYMBOL(il_power_update_mode);
 void
 il_power_initialize(struct il_priv *il)
 {
-	u16 lctl = il_pcie_link_ctl(il);
+	u16 lctl;
 
+	pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
 	il->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
 
 	il->power_data.debug_sleep_level_override = -1;
@@ -4233,7 +4234,7 @@ il_apm_init(struct il_priv *il)
 	 *    power savings, even without L1.
 	 */
 	if (il->cfg->set_l0s) {
-		lctl = il_pcie_link_ctl(il);
+		pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
 		if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
 		    PCI_CFG_LINK_CTRL_VAL_L1_EN) {
 			/* L1-ASPM enabled; disable(!) L0S  */
diff --git a/drivers/net/wireless/iwlegacy/common.h b/drivers/net/wireless/iwlegacy/common.h
index b4bb813..c9a5022 100644
--- a/drivers/net/wireless/iwlegacy/common.h
+++ b/drivers/net/wireless/iwlegacy/common.h
@@ -1829,14 +1829,6 @@ int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
  * PCI						     *
  *****************************************************/
 
-static inline u16
-il_pcie_link_ctl(struct il_priv *il)
-{
-	u16 pci_lnk_ctl;
-	pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &pci_lnk_ctl);
-	return pci_lnk_ctl;
-}
-
 void il_bg_watchdog(unsigned long data);
 u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
 __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,

[PATCH 10/12] iwlwifi: collapse wrapper for pcie_capability_read_word()

[Bjorn Helgaas]

iwl_pciexp_link_ctrl() has only one call site and no longer provides any
useful abstraction, so collapse it into the caller.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: "John W. Linville" <linville@tuxdriver.com>
CC: Johannes Berg <johannes.berg@intel.com>
CC: Wey-Yi Guy <wey-yi.w.guy@intel.com>
CC: Intel Linux Wireless <ilw@linux.intel.com>
CC: linux-wireless@vger.kernel.org
---
 drivers/net/wireless/iwlwifi/pcie/trans.c |   13 +++----------
 1 files changed, 3 insertions(+), 10 deletions(-)

diff --git a/drivers/net/wireless/iwlwifi/pcie/trans.c b/drivers/net/wireless/iwlwifi/pcie/trans.c
index fe0fffd..5cd06b3 100644
--- a/drivers/net/wireless/iwlwifi/pcie/trans.c
+++ b/drivers/net/wireless/iwlwifi/pcie/trans.c
@@ -673,18 +673,11 @@ static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN	0x01
 #define PCI_CFG_LINK_CTRL_VAL_L1_EN	0x02
 
-static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
+static void iwl_apm_config(struct iwl_trans *trans)
 {
 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
-	u16 pci_lnk_ctl;
-
-	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL,
-				  &pci_lnk_ctl);
-	return pci_lnk_ctl;
-}
+	u16 lctl;
 
-static void iwl_apm_config(struct iwl_trans *trans)
-{
 	/*
 	 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 	 * Check if BIOS (or OS) enabled L1-ASPM on this device.
@@ -693,8 +686,8 @@ static void iwl_apm_config(struct iwl_trans *trans)
 	 * If not (unlikely), enable L0S, so there is at least some
 	 *    power savings, even without L1.
 	 */
-	u16 lctl = iwl_pciexp_link_ctrl(trans);
 
+	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 	if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
 				PCI_CFG_LINK_CTRL_VAL_L1_EN) {
 		/* L1-ASPM enabled; disable(!) L0S */

[PATCH 11/12] iwlegacy: Use standard #defines for PCIe Capability ASPM fields

[Bjorn Helgaas]

Use the standard #defines rather than creating local definitions for
PCIe Capability ASPM fields.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: "John W. Linville" <linville@tuxdriver.com>
CC: Stanislaw Gruszka <sgruszka@redhat.com>
CC: linux-wireless@vger.kernel.org
---
 drivers/net/wireless/iwlegacy/4965.h   |    4 ----
 drivers/net/wireless/iwlegacy/common.c |    5 ++---
 drivers/net/wireless/iwlegacy/common.h |    4 ----
 3 files changed, 2 insertions(+), 11 deletions(-)

diff --git a/drivers/net/wireless/iwlegacy/4965.h b/drivers/net/wireless/iwlegacy/4965.h
index 2d092f3..1b15b0b 100644
--- a/drivers/net/wireless/iwlegacy/4965.h
+++ b/drivers/net/wireless/iwlegacy/4965.h
@@ -917,10 +917,6 @@ struct il4965_scd_bc_tbl {
 /* PCI registers */
 #define PCI_CFG_RETRY_TIMEOUT	0x041
 
-/* PCI register values */
-#define PCI_CFG_LINK_CTRL_VAL_L0S_EN	0x01
-#define PCI_CFG_LINK_CTRL_VAL_L1_EN	0x02
-
 #define IL4965_DEFAULT_TX_RETRY  15
 
 /* EEPROM */
diff --git a/drivers/net/wireless/iwlegacy/common.c b/drivers/net/wireless/iwlegacy/common.c
index 1811507..7e16d10 100644
--- a/drivers/net/wireless/iwlegacy/common.c
+++ b/drivers/net/wireless/iwlegacy/common.c
@@ -1186,7 +1186,7 @@ il_power_initialize(struct il_priv *il)
 	u16 lctl;
 
 	pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
-	il->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
+	il->power_data.pci_pm = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 
 	il->power_data.debug_sleep_level_override = -1;
 
@@ -4235,8 +4235,7 @@ il_apm_init(struct il_priv *il)
 	 */
 	if (il->cfg->set_l0s) {
 		pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
-		if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
-		    PCI_CFG_LINK_CTRL_VAL_L1_EN) {
+		if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
 			/* L1-ASPM enabled; disable(!) L0S  */
 			il_set_bit(il, CSR_GIO_REG,
 				   CSR_GIO_REG_VAL_L0S_ENABLED);
diff --git a/drivers/net/wireless/iwlegacy/common.h b/drivers/net/wireless/iwlegacy/common.h
index c9a5022..e181f3b 100644
--- a/drivers/net/wireless/iwlegacy/common.h
+++ b/drivers/net/wireless/iwlegacy/common.h
@@ -2426,10 +2426,6 @@ struct il_tfd {
 /* PCI registers */
 #define PCI_CFG_RETRY_TIMEOUT	0x041
 
-/* PCI register values */
-#define PCI_CFG_LINK_CTRL_VAL_L0S_EN	0x01
-#define PCI_CFG_LINK_CTRL_VAL_L1_EN	0x02
-
 struct il_rate_info {
 	u8 plcp;		/* uCode API:  RATE_6M_PLCP, etc. */
 	u8 plcp_siso;		/* uCode API:  RATE_SISO_6M_PLCP, etc. */

[PATCH 12/12] iwlwifi: Use standard #defines for PCIe Capability ASPM fields

[Bjorn Helgaas]

Use the standard #defines rather than creating local definitions for
PCIe Capability ASPM fields.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: "John W. Linville" <linville@tuxdriver.com>
CC: Johannes Berg <johannes.berg@intel.com>
CC: Wey-Yi Guy <wey-yi.w.guy@intel.com>
CC: Intel Linux Wireless <ilw@linux.intel.com>
CC: linux-wireless@vger.kernel.org
---
 drivers/net/wireless/iwlwifi/pcie/trans.c |    7 ++-----
 1 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/net/wireless/iwlwifi/pcie/trans.c b/drivers/net/wireless/iwlwifi/pcie/trans.c
index 5cd06b3..1dfa6be 100644
--- a/drivers/net/wireless/iwlwifi/pcie/trans.c
+++ b/drivers/net/wireless/iwlwifi/pcie/trans.c
@@ -670,8 +670,6 @@ static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 
 /* PCI registers */
 #define PCI_CFG_RETRY_TIMEOUT	0x041
-#define PCI_CFG_LINK_CTRL_VAL_L0S_EN	0x01
-#define PCI_CFG_LINK_CTRL_VAL_L1_EN	0x02
 
 static void iwl_apm_config(struct iwl_trans *trans)
 {
@@ -688,8 +686,7 @@ static void iwl_apm_config(struct iwl_trans *trans)
 	 */
 
 	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
-	if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
-				PCI_CFG_LINK_CTRL_VAL_L1_EN) {
+	if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
 		/* L1-ASPM enabled; disable(!) L0S */
 		iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 		dev_printk(KERN_INFO, trans->dev,
@@ -700,7 +697,7 @@ static void iwl_apm_config(struct iwl_trans *trans)
 		dev_printk(KERN_INFO, trans->dev,
 			   "L1 Disabled; Enabling L0S\n");
 	}
-	trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
+	trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 }
 
 /*

Re: [PATCH 12/12] iwlwifi: Use standard #defines for PCIe Capability ASPM fields

[Johannes Berg]

On Wed, 2012-12-05 at 13:58 -0700, Bjorn Helgaas wrote:
> Use the standard #defines rather than creating local definitions for
> PCIe Capability ASPM fields.

I'll pick up the iwlwifi ones if you want, or do you want to merge them
somewhere centrally instead?

johannes

Re: [PATCH 12/12] iwlwifi: Use standard #defines for PCIe Capability ASPM fields

[Bjorn Helgaas]

On Wed, Dec 5, 2012 at 2:04 PM, Johannes Berg <johannes@sipsolutions.net> wrote:
> On Wed, 2012-12-05 at 13:58 -0700, Bjorn Helgaas wrote:
>> Use the standard #defines rather than creating local definitions for
>> PCIe Capability ASPM fields.
>
> I'll pick up the iwlwifi ones if you want, or do you want to merge them
> somewhere centrally instead?

They do depend on a previous patch that adds the #defines to
include/uapi/linux/pci_regs.h
(http://marc.info/?l=linux-pci&m=135474107109010&w=2).

I think I'll merge at least the PCI core parts of this via my PCI tree
in the v3.8 merge window next week.  If it won't cause conflicts for
you, I could include the iwlwifi bits there, too.  If it does, at
least the #define will exist and you can merge it at your leisure.

Bjorn

Re: [PATCH 12/12] iwlwifi: Use standard #defines for PCIe Capability ASPM fields

[Johannes Berg]

On Wed, 2012-12-05 at 14:20 -0700, Bjorn Helgaas wrote:
> On Wed, Dec 5, 2012 at 2:04 PM, Johannes Berg <johannes@sipsolutions.net> wrote:
> > On Wed, 2012-12-05 at 13:58 -0700, Bjorn Helgaas wrote:
> >> Use the standard #defines rather than creating local definitions for
> >> PCIe Capability ASPM fields.
> >
> > I'll pick up the iwlwifi ones if you want, or do you want to merge them
> > somewhere centrally instead?
> 
> They do depend on a previous patch that adds the #defines to
> include/uapi/linux/pci_regs.h
> (http://marc.info/?l=linux-pci&m=135474107109010&w=2).
> 
> I think I'll merge at least the PCI core parts of this via my PCI tree
> in the v3.8 merge window next week.  If it won't cause conflicts for
> you, I could include the iwlwifi bits there, too.  If it does, at
> least the #define will exist and you can merge it at your leisure.

Ok, that's fine, feel free to include the iwlwifi bits.

Acked-by: Johannes Berg <johannes.berg@intel.com>

:)

johannes

Re: [PATCH 07/12] e1000e: Use standard #defines for PCIe Capability ASPM fields

[Jeff Kirsher]

[-- Attachment #1: Type: text/plain, Size: 1287 bytes --]

On Wed, 2012-12-05 at 13:57 -0700, Bjorn Helgaas wrote:
> Use the standard #defines for PCIe Capability ASPM fields.
> 
> Previously we used PCIE_LINK_STATE_L0S and PCIE_LINK_STATE_L1
> directly, but
> these are defined for the Linux ASPM interfaces, e.g.,
> pci_disable_link_state(), and only coincidentally match the actual
> register
> bits.  PCIE_LINK_STATE_CLKPM, also part of that interface, does not
> match
> the register bit.
> 
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> CC: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
> CC: Jesse Brandeburg <jesse.brandeburg@intel.com>
> CC: Bruce Allan <bruce.w.allan@intel.com>
> CC: Carolyn Wyborny <carolyn.wyborny@intel.com>
> CC: Don Skidmore <donald.c.skidmore@intel.com>
> CC: Greg Rose <gregory.v.rose@intel.com>
> CC: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>
> CC: Alex Duyck <alexander.h.duyck@intel.com>
> CC: John Ronciak <john.ronciak@intel.com>
> CC: e1000-devel@lists.sourceforge.net
> ---
>  drivers/net/ethernet/intel/e1000e/netdev.c |   11 +++++++++--
>  1 files changed, 9 insertions(+), 2 deletions(-) 

Thanks I will add this patch to my queue for e1000e.  Since this is
patch 7 of 12, are there PCI dependent patches in the series that need
to be applied before?

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Re: [PATCH 07/12] e1000e: Use standard #defines for PCIe Capability ASPM fields

[Bjorn Helgaas]

On Wed, Dec 5, 2012 at 3:05 PM, Jeff Kirsher
<jeffrey.t.kirsher@intel.com> wrote:
> On Wed, 2012-12-05 at 13:57 -0700, Bjorn Helgaas wrote:
>> Use the standard #defines for PCIe Capability ASPM fields.
>>
>> Previously we used PCIE_LINK_STATE_L0S and PCIE_LINK_STATE_L1
>> directly, but
>> these are defined for the Linux ASPM interfaces, e.g.,
>> pci_disable_link_state(), and only coincidentally match the actual
>> register
>> bits.  PCIE_LINK_STATE_CLKPM, also part of that interface, does not
>> match
>> the register bit.
>>
>> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>> CC: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
>> CC: Jesse Brandeburg <jesse.brandeburg@intel.com>
>> CC: Bruce Allan <bruce.w.allan@intel.com>
>> CC: Carolyn Wyborny <carolyn.wyborny@intel.com>
>> CC: Don Skidmore <donald.c.skidmore@intel.com>
>> CC: Greg Rose <gregory.v.rose@intel.com>
>> CC: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>
>> CC: Alex Duyck <alexander.h.duyck@intel.com>
>> CC: John Ronciak <john.ronciak@intel.com>
>> CC: e1000-devel@lists.sourceforge.net
>> ---
>>  drivers/net/ethernet/intel/e1000e/netdev.c |   11 +++++++++--
>>  1 files changed, 9 insertions(+), 2 deletions(-)
>
> Thanks I will add this patch to my queue for e1000e.  Since this is
> patch 7 of 12, are there PCI dependent patches in the series that need
> to be applied before?

Yes.  It does depend on a previous patch that adds the #defines to
include/uapi/linux/pci_regs.h
(http://marc.info/?l=linux-pci&m=135474107109010&w=2).

I plan to merge that during the v3.8 merge window, so you can merge it
after that.  Or, if it won't cause you conflicts, I can include the
e1000e change in my PCI tree.

Bjorn

Re: [PATCH 07/12] e1000e: Use standard #defines for PCIe Capability ASPM fields

[Jeff Kirsher]

[-- Attachment #1: Type: text/plain, Size: 2047 bytes --]

On Wed, 2012-12-05 at 15:07 -0700, Bjorn Helgaas wrote:
> On Wed, Dec 5, 2012 at 3:05 PM, Jeff Kirsher
> <jeffrey.t.kirsher@intel.com> wrote:
> > On Wed, 2012-12-05 at 13:57 -0700, Bjorn Helgaas wrote:
> >> Use the standard #defines for PCIe Capability ASPM fields.
> >>
> >> Previously we used PCIE_LINK_STATE_L0S and PCIE_LINK_STATE_L1
> >> directly, but
> >> these are defined for the Linux ASPM interfaces, e.g.,
> >> pci_disable_link_state(), and only coincidentally match the actual
> >> register
> >> bits.  PCIE_LINK_STATE_CLKPM, also part of that interface, does not
> >> match
> >> the register bit.
> >>
> >> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> >> CC: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
> >> CC: Jesse Brandeburg <jesse.brandeburg@intel.com>
> >> CC: Bruce Allan <bruce.w.allan@intel.com>
> >> CC: Carolyn Wyborny <carolyn.wyborny@intel.com>
> >> CC: Don Skidmore <donald.c.skidmore@intel.com>
> >> CC: Greg Rose <gregory.v.rose@intel.com>
> >> CC: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>
> >> CC: Alex Duyck <alexander.h.duyck@intel.com>
> >> CC: John Ronciak <john.ronciak@intel.com>
> >> CC: e1000-devel@lists.sourceforge.net
> >> ---
> >>  drivers/net/ethernet/intel/e1000e/netdev.c |   11 +++++++++--
> >>  1 files changed, 9 insertions(+), 2 deletions(-)
> >
> > Thanks I will add this patch to my queue for e1000e.  Since this is
> > patch 7 of 12, are there PCI dependent patches in the series that need
> > to be applied before?
> 
> Yes.  It does depend on a previous patch that adds the #defines to
> include/uapi/linux/pci_regs.h
> (http://marc.info/?l=linux-pci&m=135474107109010&w=2).
> 
> I plan to merge that during the v3.8 merge window, so you can merge it
> after that.  Or, if it won't cause you conflicts, I can include the
> e1000e change in my PCI tree.
> 
> Bjorn

yeah, it does not apply cleanly (because of patches currently in the
queue from Bruce).  So I will take care of pushing your e1000e patch
through Dave's tree.

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RE: [PATCH 05/12] PCI: Add standard PCIe Capability Link ASPM field names

[Kaneshige, Kenji]

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Re: [PATCH 09/12] iwlegacy: collapse wrapper for pcie_capability_read_word()

[Stanislaw Gruszka]

On Wed, Dec 05, 2012 at 01:58:06PM -0700, Bjorn Helgaas wrote:
> il_pcie_link_ctl() has only one call site and no longer provides any useful
> abstraction, so collapse it into the caller.
> 
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> CC: "John W. Linville" <linville@tuxdriver.com>
> CC: Stanislaw Gruszka <sgruszka@redhat.com>
Acked-by: Stanislaw Gruszka <sgruszka@redhat.com>

Re: [PATCH 11/12] iwlegacy: Use standard #defines for PCIe Capability ASPM fields

[Stanislaw Gruszka]

On Wed, Dec 05, 2012 at 01:58:16PM -0700, Bjorn Helgaas wrote:
> Use the standard #defines rather than creating local definitions for
> PCIe Capability ASPM fields.
> 
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> CC: "John W. Linville" <linville@tuxdriver.com>
> CC: Stanislaw Gruszka <sgruszka@redhat.com>
Acked-by: Stanislaw Gruszka <sgruszka@redhat.com>

Re: [PATCH 04/12] [SCSI] qla2xxx: Use standard PCIe Capability Link register field names

[Saurav Kashyap]

Acked-by: Saurav Kashyap <saurav.kashyap@qlogic.com>

Thanks,
~Saurav



>Use the standard #defines for PCIe Link Capability register fields
>rather than bare numbers.  This also uses the new PCI Express Capability
>accessor rather than reading the capability directly.
>
>Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>CC: Andrew Vasquez <andrew.vasquez@qlogic.com>
>CC: linux-driver@qlogic.com
>CC: "James E.J. Bottomley" <JBottomley@parallels.com>
>CC: linux-scsi@vger.kernel.org
>---
> drivers/scsi/qla2xxx/qla_os.c |   14 +++++---------
> 1 files changed, 5 insertions(+), 9 deletions(-)
>
>diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c
>index d501bf5..b5d070f 100644
>--- a/drivers/scsi/qla2xxx/qla_os.c
>+++ b/drivers/scsi/qla2xxx/qla_os.c
>@@ -480,18 +480,14 @@ qla24xx_pci_info_str(struct scsi_qla_host *vha,
>char *str)
>       static char *pci_bus_modes[] = { "33", "66", "100", "133", };
>       struct qla_hw_data *ha = vha->hw;
>       uint32_t pci_bus;
>-      int pcie_reg;
>
>-      pcie_reg = pci_pcie_cap(ha->pdev);
>-      if (pcie_reg) {
>+      if (pci_is_pcie(ha->pdev)) {
>               char lwstr[6];
>-              uint16_t pcie_lstat, lspeed, lwidth;
>+              uint32_t lstat, lspeed, lwidth;
>
>-              pcie_reg += PCI_EXP_LNKCAP;
>-              pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
>-              lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
>-              lwidth = (pcie_lstat &
>-                  (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
>+              pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
>+              lspeed = lstat & PCI_EXP_LNKCAP_SLS;
>+              lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
>
>               strcpy(str, "PCIe (");
>               if (lspeed == 1)
>
>--
>To unsubscribe from this list: send the line "unsubscribe linux-scsi" in
>the body of a message to majordomo@vger.kernel.org
>More majordomo info at  http://vger.kernel.org/majordomo-info.html
>


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Re: [PATCH 06/12] cxgb3: Use standard #defines for PCIe Capability ASPM fields

[David Miller]

From: Bjorn Helgaas <bhelgaas@google.com>
Date: Wed, 05 Dec 2012 13:57:50 -0700

> Use the standard #defines rather than bare numbers for PCIe Capability
> ASPM fields.
> 
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

This seems to depend upon another patch which presumably adds the
define of this new macro to a PCI header file.  So I can't apply
this to my tree.

Just merge it wherever the dependency is:

Acked-by: David S. Miller <davem@davemloft.net>

Re: [PATCH 01/12] PCI: Add and use standard PCI-X Capability register names

[Bjorn Helgaas]

On Wed, Dec 5, 2012 at 1:57 PM, Bjorn Helgaas <bhelgaas@google.com> wrote:
> Add and use #defines for PCI-X Capability registers and fields.
> Note that the PCI-X Capability has a different layout for
> type 0 (endpoint) and type 1 (bridge) devices.

I added the following patches from this series to my -next branch and
plan to merge them in the v2.8 merge window next week.  The non-PCI
ones have been acked and the maintainers are OK with merging them
through the PCI tree.

    * pci/bjorn-pcie-cap:
      iwlwifi: Use standard #defines for PCIe Capability ASPM fields
      iwlwifi: collapse wrapper for pcie_capability_read_word()
      iwlegacy: Use standard #defines for PCIe Capability ASPM fields
      iwlegacy: collapse wrapper for pcie_capability_read_word()
      cxgb3: Use standard #defines for PCIe Capability ASPM fields
      PCI: Add standard PCIe Capability Link ASPM field names
      PCI/portdrv: Use PCI Express Capability accessors
      PCI: Use standard PCIe Capability Link register field names
      PCI: Add and use standard PCI-X Capability register names

I did not merge the following patches.  They depend on one of the
patches above and the e1000e one conflicts with other patches in the
queue.  So these can be merged at any time after v3.8-rc1 (or even
before -rc1 as long as it's after the PCI -next branch is merged).

    ath9k: Use standard #defines for PCIe Capability ASPM fields
    e1000e: Use standard #defines for PCIe Capability ASPM fields
    [SCSI] qla2xxx: Use standard PCIe Capability Link register field names

Bjorn

Re: [PATCH 04/12] [SCSI] qla2xxx: Use standard PCIe Capability Link register field names

[Giridhar Malavali]

Acked-by: Giridhar Malavali

On 12/7/12 12:17 AM, "Saurav Kashyap" <saurav.kashyap@qlogic.com> wrote:

>Acked-by: Saurav Kashyap <saurav.kashyap@qlogic.com>
>
>Thanks,
>~Saurav
>
>
>
>>Use the standard #defines for PCIe Link Capability register fields
>>rather than bare numbers.  This also uses the new PCI Express Capability
>>accessor rather than reading the capability directly.
>>
>>Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>>CC: Andrew Vasquez <andrew.vasquez@qlogic.com>
>>CC: linux-driver@qlogic.com
>>CC: "James E.J. Bottomley" <JBottomley@parallels.com>
>>CC: linux-scsi@vger.kernel.org
>>---
>> drivers/scsi/qla2xxx/qla_os.c |   14 +++++---------
>> 1 files changed, 5 insertions(+), 9 deletions(-)
>>
>>diff --git a/drivers/scsi/qla2xxx/qla_os.c
>>b/drivers/scsi/qla2xxx/qla_os.c
>>index d501bf5..b5d070f 100644
>>--- a/drivers/scsi/qla2xxx/qla_os.c
>>+++ b/drivers/scsi/qla2xxx/qla_os.c
>>@@ -480,18 +480,14 @@ qla24xx_pci_info_str(struct scsi_qla_host *vha,
>>char *str)
>> 	static char *pci_bus_modes[] = { "33", "66", "100", "133", };
>> 	struct qla_hw_data *ha = vha->hw;
>> 	uint32_t pci_bus;
>>-	int pcie_reg;
>> 
>>-	pcie_reg = pci_pcie_cap(ha->pdev);
>>-	if (pcie_reg) {
>>+	if (pci_is_pcie(ha->pdev)) {
>> 		char lwstr[6];
>>-		uint16_t pcie_lstat, lspeed, lwidth;
>>+		uint32_t lstat, lspeed, lwidth;
>> 
>>-		pcie_reg += PCI_EXP_LNKCAP;
>>-		pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
>>-		lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
>>-		lwidth = (pcie_lstat &
>>-		    (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
>>+		pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
>>+		lspeed = lstat & PCI_EXP_LNKCAP_SLS;
>>+		lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
>> 
>> 		strcpy(str, "PCIe (");
>> 		if (lspeed == 1)
>>
>>--
>>To unsubscribe from this list: send the line "unsubscribe linux-scsi" in
>>the body of a message to majordomo@vger.kernel.org
>>More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>
>

Re: [PATCH 04/12] [SCSI] qla2xxx: Use standard PCIe Capability Link register field names

[Bjorn Helgaas]

Ping.  I didn't push this through my tree because I didn't want to
create conflicts with other changes to this file.  But I think this
can be merged any time.

On Fri, Dec 7, 2012 at 3:29 PM, Giridhar Malavali
<giridhar.malavali@qlogic.com> wrote:
> Acked-by: Giridhar Malavali
>
> On 12/7/12 12:17 AM, "Saurav Kashyap" <saurav.kashyap@qlogic.com> wrote:
>
>>Acked-by: Saurav Kashyap <saurav.kashyap@qlogic.com>
>>
>>Thanks,
>>~Saurav
>>
>>
>>
>>>Use the standard #defines for PCIe Link Capability register fields
>>>rather than bare numbers.  This also uses the new PCI Express Capability
>>>accessor rather than reading the capability directly.
>>>
>>>Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>>>CC: Andrew Vasquez <andrew.vasquez@qlogic.com>
>>>CC: linux-driver@qlogic.com
>>>CC: "James E.J. Bottomley" <JBottomley@parallels.com>
>>>CC: linux-scsi@vger.kernel.org
>>>---
>>> drivers/scsi/qla2xxx/qla_os.c |   14 +++++---------
>>> 1 files changed, 5 insertions(+), 9 deletions(-)
>>>
>>>diff --git a/drivers/scsi/qla2xxx/qla_os.c
>>>b/drivers/scsi/qla2xxx/qla_os.c
>>>index d501bf5..b5d070f 100644
>>>--- a/drivers/scsi/qla2xxx/qla_os.c
>>>+++ b/drivers/scsi/qla2xxx/qla_os.c
>>>@@ -480,18 +480,14 @@ qla24xx_pci_info_str(struct scsi_qla_host *vha,
>>>char *str)
>>>      static char *pci_bus_modes[] = { "33", "66", "100", "133", };
>>>      struct qla_hw_data *ha = vha->hw;
>>>      uint32_t pci_bus;
>>>-     int pcie_reg;
>>>
>>>-     pcie_reg = pci_pcie_cap(ha->pdev);
>>>-     if (pcie_reg) {
>>>+     if (pci_is_pcie(ha->pdev)) {
>>>              char lwstr[6];
>>>-             uint16_t pcie_lstat, lspeed, lwidth;
>>>+             uint32_t lstat, lspeed, lwidth;
>>>
>>>-             pcie_reg += PCI_EXP_LNKCAP;
>>>-             pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
>>>-             lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
>>>-             lwidth = (pcie_lstat &
>>>-                 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
>>>+             pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
>>>+             lspeed = lstat & PCI_EXP_LNKCAP_SLS;
>>>+             lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
>>>
>>>              strcpy(str, "PCIe (");
>>>              if (lspeed == 1)
>>>
>>>--
>>>To unsubscribe from this list: send the line "unsubscribe linux-scsi" in
>>>the body of a message to majordomo@vger.kernel.org
>>>More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>
>>
>
>

Re: [PATCH 04/12] [SCSI] qla2xxx: Use standard PCIe Capability Link register field names

[Bjorn Helgaas]

I haven't heard anything, so I'm going to push this through the PCI
tree.  Let me know if anybody objects or would like to handle it
differently.

On Mon, Dec 17, 2012 at 12:21 PM, Bjorn Helgaas <bhelgaas@google.com> wrote:
> Ping.  I didn't push this through my tree because I didn't want to
> create conflicts with other changes to this file.  But I think this
> can be merged any time.
>
> On Fri, Dec 7, 2012 at 3:29 PM, Giridhar Malavali
> <giridhar.malavali@qlogic.com> wrote:
>> Acked-by: Giridhar Malavali
>>
>> On 12/7/12 12:17 AM, "Saurav Kashyap" <saurav.kashyap@qlogic.com> wrote:
>>
>>>Acked-by: Saurav Kashyap <saurav.kashyap@qlogic.com>
>>>
>>>Thanks,
>>>~Saurav
>>>
>>>
>>>
>>>>Use the standard #defines for PCIe Link Capability register fields
>>>>rather than bare numbers.  This also uses the new PCI Express Capability
>>>>accessor rather than reading the capability directly.
>>>>
>>>>Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>>>>CC: Andrew Vasquez <andrew.vasquez@qlogic.com>
>>>>CC: linux-driver@qlogic.com
>>>>CC: "James E.J. Bottomley" <JBottomley@parallels.com>
>>>>CC: linux-scsi@vger.kernel.org
>>>>---
>>>> drivers/scsi/qla2xxx/qla_os.c |   14 +++++---------
>>>> 1 files changed, 5 insertions(+), 9 deletions(-)
>>>>
>>>>diff --git a/drivers/scsi/qla2xxx/qla_os.c
>>>>b/drivers/scsi/qla2xxx/qla_os.c
>>>>index d501bf5..b5d070f 100644
>>>>--- a/drivers/scsi/qla2xxx/qla_os.c
>>>>+++ b/drivers/scsi/qla2xxx/qla_os.c
>>>>@@ -480,18 +480,14 @@ qla24xx_pci_info_str(struct scsi_qla_host *vha,
>>>>char *str)
>>>>      static char *pci_bus_modes[] = { "33", "66", "100", "133", };
>>>>      struct qla_hw_data *ha = vha->hw;
>>>>      uint32_t pci_bus;
>>>>-     int pcie_reg;
>>>>
>>>>-     pcie_reg = pci_pcie_cap(ha->pdev);
>>>>-     if (pcie_reg) {
>>>>+     if (pci_is_pcie(ha->pdev)) {
>>>>              char lwstr[6];
>>>>-             uint16_t pcie_lstat, lspeed, lwidth;
>>>>+             uint32_t lstat, lspeed, lwidth;
>>>>
>>>>-             pcie_reg += PCI_EXP_LNKCAP;
>>>>-             pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
>>>>-             lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
>>>>-             lwidth = (pcie_lstat &
>>>>-                 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
>>>>+             pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
>>>>+             lspeed = lstat & PCI_EXP_LNKCAP_SLS;
>>>>+             lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
>>>>
>>>>              strcpy(str, "PCIe (");
>>>>              if (lspeed == 1)
>>>>
>>>>--
>>>>To unsubscribe from this list: send the line "unsubscribe linux-scsi" in
>>>>the body of a message to majordomo@vger.kernel.org
>>>>More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>>
>>>
>>
>>

Re: [PATCH 07/12] e1000e: Use standard #defines for PCIe Capability ASPM fields

[Bjorn Helgaas]

On Wed, Dec 5, 2012 at 3:24 PM, Jeff Kirsher
<jeffrey.t.kirsher@intel.com> wrote:
> On Wed, 2012-12-05 at 15:07 -0700, Bjorn Helgaas wrote:
>> On Wed, Dec 5, 2012 at 3:05 PM, Jeff Kirsher
>> <jeffrey.t.kirsher@intel.com> wrote:
>> > On Wed, 2012-12-05 at 13:57 -0700, Bjorn Helgaas wrote:
>> >> Use the standard #defines for PCIe Capability ASPM fields.
>> >>
>> >> Previously we used PCIE_LINK_STATE_L0S and PCIE_LINK_STATE_L1
>> >> directly, but
>> >> these are defined for the Linux ASPM interfaces, e.g.,
>> >> pci_disable_link_state(), and only coincidentally match the actual
>> >> register
>> >> bits.  PCIE_LINK_STATE_CLKPM, also part of that interface, does not
>> >> match
>> >> the register bit.
>> >>
>> >> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>> >> CC: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
>> >> CC: Jesse Brandeburg <jesse.brandeburg@intel.com>
>> >> CC: Bruce Allan <bruce.w.allan@intel.com>
>> >> CC: Carolyn Wyborny <carolyn.wyborny@intel.com>
>> >> CC: Don Skidmore <donald.c.skidmore@intel.com>
>> >> CC: Greg Rose <gregory.v.rose@intel.com>
>> >> CC: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>
>> >> CC: Alex Duyck <alexander.h.duyck@intel.com>
>> >> CC: John Ronciak <john.ronciak@intel.com>
>> >> CC: e1000-devel@lists.sourceforge.net
>> >> ---
>> >>  drivers/net/ethernet/intel/e1000e/netdev.c |   11 +++++++++--
>> >>  1 files changed, 9 insertions(+), 2 deletions(-)
>> >
>> > Thanks I will add this patch to my queue for e1000e.  Since this is
>> > patch 7 of 12, are there PCI dependent patches in the series that need
>> > to be applied before?
>>
>> Yes.  It does depend on a previous patch that adds the #defines to
>> include/uapi/linux/pci_regs.h
>> (http://marc.info/?l=linux-pci&m=135474107109010&w=2).
>>
>> I plan to merge that during the v3.8 merge window, so you can merge it
>> after that.  Or, if it won't cause you conflicts, I can include the
>> e1000e change in my PCI tree.
>>
>> Bjorn
>
> yeah, it does not apply cleanly (because of patches currently in the
> queue from Bruce).  So I will take care of pushing your e1000e patch
> through Dave's tree.

The pci_regs.h change this depends on appeared in v3.8-rc2, so this
patch can be merged any time, at least as far as that particular
issue.

Re: [PATCH 04/12] [SCSI] qla2xxx: Use standard PCIe Capability Link register field names

[Bjorn Helgaas]

Sorry, I said I was going to push this through my PCI tree, but I
forgot all about it.  I put it (finally) in my pci/misc branch, and
will merge it during the v3.13 merge window.

On Fri, Jan 4, 2013 at 12:31 PM, Bjorn Helgaas <bhelgaas@google.com> wrote:
> I haven't heard anything, so I'm going to push this through the PCI
> tree.  Let me know if anybody objects or would like to handle it
> differently.
>
> On Mon, Dec 17, 2012 at 12:21 PM, Bjorn Helgaas <bhelgaas@google.com> wrote:
>> Ping.  I didn't push this through my tree because I didn't want to
>> create conflicts with other changes to this file.  But I think this
>> can be merged any time.
>>
>> On Fri, Dec 7, 2012 at 3:29 PM, Giridhar Malavali
>> <giridhar.malavali@qlogic.com> wrote:
>>> Acked-by: Giridhar Malavali
>>>
>>> On 12/7/12 12:17 AM, "Saurav Kashyap" <saurav.kashyap@qlogic.com> wrote:
>>>
>>>>Acked-by: Saurav Kashyap <saurav.kashyap@qlogic.com>
>>>>
>>>>Thanks,
>>>>~Saurav
>>>>
>>>>
>>>>
>>>>>Use the standard #defines for PCIe Link Capability register fields
>>>>>rather than bare numbers.  This also uses the new PCI Express Capability
>>>>>accessor rather than reading the capability directly.
>>>>>
>>>>>Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>>>>>CC: Andrew Vasquez <andrew.vasquez@qlogic.com>
>>>>>CC: linux-driver@qlogic.com
>>>>>CC: "James E.J. Bottomley" <JBottomley@parallels.com>
>>>>>CC: linux-scsi@vger.kernel.org
>>>>>---
>>>>> drivers/scsi/qla2xxx/qla_os.c |   14 +++++---------
>>>>> 1 files changed, 5 insertions(+), 9 deletions(-)
>>>>>
>>>>>diff --git a/drivers/scsi/qla2xxx/qla_os.c
>>>>>b/drivers/scsi/qla2xxx/qla_os.c
>>>>>index d501bf5..b5d070f 100644
>>>>>--- a/drivers/scsi/qla2xxx/qla_os.c
>>>>>+++ b/drivers/scsi/qla2xxx/qla_os.c
>>>>>@@ -480,18 +480,14 @@ qla24xx_pci_info_str(struct scsi_qla_host *vha,
>>>>>char *str)
>>>>>      static char *pci_bus_modes[] = { "33", "66", "100", "133", };
>>>>>      struct qla_hw_data *ha = vha->hw;
>>>>>      uint32_t pci_bus;
>>>>>-     int pcie_reg;
>>>>>
>>>>>-     pcie_reg = pci_pcie_cap(ha->pdev);
>>>>>-     if (pcie_reg) {
>>>>>+     if (pci_is_pcie(ha->pdev)) {
>>>>>              char lwstr[6];
>>>>>-             uint16_t pcie_lstat, lspeed, lwidth;
>>>>>+             uint32_t lstat, lspeed, lwidth;
>>>>>
>>>>>-             pcie_reg += PCI_EXP_LNKCAP;
>>>>>-             pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
>>>>>-             lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
>>>>>-             lwidth = (pcie_lstat &
>>>>>-                 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
>>>>>+             pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
>>>>>+             lspeed = lstat & PCI_EXP_LNKCAP_SLS;
>>>>>+             lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
>>>>>
>>>>>              strcpy(str, "PCIe (");
>>>>>              if (lspeed == 1)
>>>>>
>>>>>--
>>>>>To unsubscribe from this list: send the line "unsubscribe linux-scsi" in
>>>>>the body of a message to majordomo@vger.kernel.org
>>>>>More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>>>
>>>>
>>>
>>>