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* [PATCH 01/12] PCI: Add and use standard PCI-X Capability register names
@ 2012-12-05 20:57 Bjorn Helgaas
  2012-12-05 20:57 ` [PATCH 02/12] PCI: Use standard PCIe Capability Link register field names Bjorn Helgaas
                   ` (11 more replies)
  0 siblings, 12 replies; 29+ messages in thread
From: Bjorn Helgaas @ 2012-12-05 20:57 UTC (permalink / raw)
  To: linux-pci; +Cc: Matthew Wilcox

Add and use #defines for PCI-X Capability registers and fields.
Note that the PCI-X Capability has a different layout for
type 0 (endpoint) and type 1 (bridge) devices.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Matthew Wilcox <willy@linux.intel.com>
---
 drivers/pci/probe.c           |   15 +++++++++------
 include/uapi/linux/pci_regs.h |   15 ++++++++++++++-
 2 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index ec909af..81d0667 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -579,14 +579,16 @@ static void pci_set_bus_speed(struct pci_bus *bus)
 	if (pos) {
 		u16 status;
 		enum pci_bus_speed max;
-		pci_read_config_word(bridge, pos + 2, &status);
 
-		if (status & 0x8000) {
+		pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
+				     &status);
+
+		if (status & PCI_X_SSTATUS_533MHZ) {
 			max = PCI_SPEED_133MHz_PCIX_533;
-		} else if (status & 0x4000) {
+		} else if (status & PCI_X_SSTATUS_266MHZ) {
 			max = PCI_SPEED_133MHz_PCIX_266;
-		} else if (status & 0x0002) {
-			if (((status >> 12) & 0x3) == 2) {
+		} else if (status & PCI_X_SSTATUS_133MHZ) {
+			if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) {
 				max = PCI_SPEED_133MHz_PCIX_ECC;
 			} else {
 				max = PCI_SPEED_133MHz_PCIX;
@@ -596,7 +598,8 @@ static void pci_set_bus_speed(struct pci_bus *bus)
 		}
 
 		bus->max_bus_speed = max;
-		bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
+		bus->cur_bus_speed = pcix_bus_speed[
+			(status & PCI_X_SSTATUS_FREQ) >> 6];
 
 		return;
 	}
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 20ae747..4cca834 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -349,7 +349,7 @@
 #define  PCI_AF_STATUS_TP	0x01
 #define PCI_CAP_AF_SIZEOF	6	/* size of AF registers */
 
-/* PCI-X registers */
+/* PCI-X registers (Type 0 (non-bridge) devices) */
 
 #define PCI_X_CMD		2	/* Modes & Features */
 #define  PCI_X_CMD_DPERR_E	0x0001	/* Data Parity Error Recovery Enable */
@@ -389,6 +389,19 @@
 #define PCI_CAP_PCIX_SIZEOF_V1	24	/* size for Version 1 */
 #define PCI_CAP_PCIX_SIZEOF_V2	PCI_CAP_PCIX_SIZEOF_V1	/* Same for v2 */
 
+/* PCI-X registers (Type 1 (bridge) devices) */
+
+#define PCI_X_BRIDGE_SSTATUS	2	/* Secondary Status */
+#define  PCI_X_SSTATUS_64BIT	0x0001	/* Secondary AD interface is 64 bits */
+#define  PCI_X_SSTATUS_133MHZ	0x0002	/* 133 MHz capable */
+#define  PCI_X_SSTATUS_FREQ	0x03c0	/* Secondary Bus Mode and Frequency */
+#define  PCI_X_SSTATUS_VERS	0x3000	/* PCI-X Capability Version */
+#define  PCI_X_SSTATUS_V1	0x1000	/* Mode 2, not Mode 1 */
+#define  PCI_X_SSTATUS_V2	0x2000	/* Mode 1 or Modes 1 and 2 */
+#define  PCI_X_SSTATUS_266MHZ	0x4000	/* 266 MHz capable */
+#define  PCI_X_SSTATUS_533MHZ	0x8000	/* 533 MHz capable */
+#define PCI_X_BRIDGE_STATUS	4	/* Bridge Status */
+
 /* PCI Bridge Subsystem ID registers */
 
 #define PCI_SSVID_VENDOR_ID     4	/* PCI-Bridge subsystem vendor id register */


^ permalink raw reply related	[flat|nested] 29+ messages in thread
end of thread, other threads:[~2013-09-06 17:29 UTC | newest]

Thread overview: 29+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-12-05 20:57 [PATCH 01/12] PCI: Add and use standard PCI-X Capability register names Bjorn Helgaas
2012-12-05 20:57 ` [PATCH 02/12] PCI: Use standard PCIe Capability Link register field names Bjorn Helgaas
2012-12-05 20:57 ` [PATCH 03/12] PCI/portdrv: Use PCI Express Capability accessors Bjorn Helgaas
2012-12-05 20:57 ` [PATCH 04/12] [SCSI] qla2xxx: Use standard PCIe Capability Link register field names Bjorn Helgaas
2012-12-07  8:17   ` Saurav Kashyap
2012-12-07 22:29     ` Giridhar Malavali
2012-12-17 19:21       ` Bjorn Helgaas
2013-01-04 19:31         ` Bjorn Helgaas
2013-09-06 17:29           ` Bjorn Helgaas
2012-12-05 20:57 ` [PATCH 05/12] PCI: Add standard PCIe Capability Link ASPM " Bjorn Helgaas
2012-12-06  2:29   ` Kaneshige, Kenji
2012-12-05 20:57 ` [PATCH 06/12] cxgb3: Use standard #defines for PCIe Capability ASPM fields Bjorn Helgaas
2012-12-07 17:51   ` David Miller
2012-12-05 20:57 ` [PATCH 07/12] e1000e: " Bjorn Helgaas
2012-12-05 22:05   ` Jeff Kirsher
2012-12-05 22:07     ` Bjorn Helgaas
2012-12-05 22:24       ` Jeff Kirsher
2013-01-04 19:33         ` Bjorn Helgaas
2012-12-05 20:58 ` [PATCH 08/12] ath9k: " Bjorn Helgaas
2012-12-05 20:58 ` [PATCH 09/12] iwlegacy: collapse wrapper for pcie_capability_read_word() Bjorn Helgaas
2012-12-06  8:19   ` Stanislaw Gruszka
2012-12-05 20:58 ` [PATCH 10/12] iwlwifi: " Bjorn Helgaas
2012-12-05 20:58 ` [PATCH 11/12] iwlegacy: Use standard #defines for PCIe Capability ASPM fields Bjorn Helgaas
2012-12-06  8:20   ` Stanislaw Gruszka
2012-12-05 20:58 ` [PATCH 12/12] iwlwifi: " Bjorn Helgaas
2012-12-05 21:04   ` Johannes Berg
2012-12-05 21:20     ` Bjorn Helgaas
2012-12-05 21:26       ` Johannes Berg
2012-12-07 18:35 ` [PATCH 01/12] PCI: Add and use standard PCI-X Capability register names Bjorn Helgaas

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