From: Yijing Wang <wangyijing@huawei.com>
To: Bjorn Helgaas <bhelgaas@google.com>
Cc: <linux-pci@vger.kernel.org>, Hanjun Guo <guohanjun@huawei.com>,
<jiang.liu@huawei.com>, Yijing Wang <wangyijing@huawei.com>
Subject: [PATCH 0/7] Add hostbridge resource release to support root bus hotplug in IA64
Date: Sat, 27 Apr 2013 17:12:22 +0800 [thread overview]
Message-ID: <1367053949-38424-1-git-send-email-wangyijing@huawei.com> (raw)
Hi Bjron,
This patchset mainly to add hostbridge resource release to support root bus hotplug
in IA64. Just based your suggestion, link:http://marc.info/?l=linux-pci&m=134506155529536&w=2
I'm very sorry to send the new version patchset late. Currently, hotplug root bus code has been
in kernel, But in IA64, lack the hostbridge resource code. So we cannot hot add root bus because
resource confict report.
This patchset based your pci-next branch code.
Jiang Liu (1):
PCI/IA64: fix memleak for create pci root bus fail
Yijing Wang (6):
PCI/X86: fix always use info->res[0] to store _CRS resource when
pci=nocrs set
PCI/IA64: SN: remove sn_pci_window_fixup()
PCI/IA64: make pci_root_info holds pci hostbridge resources
PCI/IA64: Allocate pci_root_info instead of using stack
PCI/IA64: add host bridge resource release for _CRS path
PCI/IA64: introduce probe_pci_root_info() to manage _CRS resource
arch/ia64/include/asm/pci.h | 20 +++-
arch/ia64/pci/pci.c | 221 +++++++++++++++++++++++++++--------------
arch/ia64/sn/kernel/io_init.c | 106 +++++++-------------
arch/x86/pci/acpi.c | 7 +-
4 files changed, 199 insertions(+), 155 deletions(-)
next reply other threads:[~2013-04-27 9:14 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-27 9:12 Yijing Wang [this message]
2013-04-27 9:12 ` [PATCH 1/7] PCI/X86: fix always use info->res[0] to store _CRS resource when pci=nocrs set Yijing Wang
2013-04-27 9:12 ` [PATCH 2/7] PCI/IA64: SN: remove sn_pci_window_fixup() Yijing Wang
2013-04-27 9:12 ` [PATCH 3/7] PCI/IA64: make pci_root_info holds pci hostbridge resources Yijing Wang
2013-04-27 9:12 ` [PATCH 4/7] PCI/IA64: Allocate pci_root_info instead of using stack Yijing Wang
2013-04-27 9:12 ` [PATCH 5/7] PCI/IA64: fix memleak for create pci root bus fail Yijing Wang
2013-04-27 9:12 ` [PATCH 6/7] PCI/IA64: add host bridge resource release for _CRS path Yijing Wang
2013-04-27 9:12 ` [PATCH 7/7] PCI/IA64: introduce probe_pci_root_info() to manage _CRS resource Yijing Wang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1367053949-38424-1-git-send-email-wangyijing@huawei.com \
--to=wangyijing@huawei.com \
--cc=bhelgaas@google.com \
--cc=guohanjun@huawei.com \
--cc=jiang.liu@huawei.com \
--cc=linux-pci@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).