[PATCH -v4 0/8] Add hostbridge resource release to support root bus hotplug in IA64

[PATCH -v4 0/8] Add hostbridge resource release to support root bus hotplug in IA64

[Yijing Wang]

v3->v4: fix memory allocation problem and use dev_err instead of pr_err follow Bjorn's suggestion.
        Also add some SGI folks cc for the first two SN related patches.
v2->v3: remove "PCI/X86: fix always use info->res[0] to store _CRS resource when pci=nocrs set" 
		from this patchset, and update some changes about remove pci_window from pci_controller in IA64.
v1->v2: update the patchset description in this cover letter.

Hi Bjorn,
   I update this patchset description, and add some MMIO and dmesg info in order to describe
this problem more clearly. I hope it can make you review this patch easier.

Part1: clean up pci_window related code in IA64:SN, arch/ia64/sn/kernel/io_init.c
  PCI/IA64: SN: remove sn_pci_window_fixup()
  PCI/IA64: SN: use normal resource instead of pci_window

Part2: embeded pci hostbridge resource into pci_root_info and rework related code in arch/ia64/pci/pci.c
  PCI/IA64: embed pci hostbridge resources into pci_root_info
  PCI/IA64: Allocate pci_root_info instead of using stack

Part3: add hostbridge resource release to support root bus hotpug in IA64
  PCI/IA64: fix memleak for create pci root bus fail
  PCI/IA64: add host bridge resource release for _CRS path
  PCI/IA64: introduce probe_pci_root_info() to manage  _CRS resource

The main idea about this patchset based Bjorn's suggestion at http://marc.info/?l=linux-pci&m=134506155529536&w=2

Before applied this patchset, there is a problem when we do root bus hotplug in IA64. Because
we do not release MMIO and ioport resource occupied by root bus.

1. Before hot remove pci root bus

-+-[0000:40]-+-00.0-[0000:41]--
 |           +-01.0-[0000:42]--+-00.0  Intel Corporation 82576 Gigabit Network Connection
 |           |                 \-00.1  Intel Corporation 82576 Gigabit Network Connection
 |           +-03.0-[0000:43]----00.0  LSI Logic / Symbios Logic SAS1064ET PCI-Express Fusion-MPT SAS
 |           +-04.0-[0000:44]--
 |           +-05.0-[0000:45]--
 |           +-07.0-[0000:46]--+-00.0  Intel Corporation 82576 Gigabit Network Connection
 |           |                 \-00.1  Intel Corporation 82576 Gigabit Network Connection
 |           +-0d.0  Intel Corporation Device 343a
 |           +-0d.1  Intel Corporation Device 343b
 |           +-0d.7  Intel Corporation Device 341b
 [....snip.....]
 |           +-16.3  Intel Corporation 5520/5500/X58 Chipset QuickData Technology Device
 |           \-16.7  Intel Corporation 5520/5500/X58 Chipset QuickData Technology Device
 \-[0000:00]-+-00.0  Intel Corporation 5520/5500/X58 I/O Hub to ESI Port
             +-01.0-[0000:01]--+-00.0  Intel Corporation 82576 Gigabit Network Connection
             |                 \-00.1  Intel Corporation 82576 Gigabit Network Connection
             +-03.0-[0000:02]----00.0  LSI Logic / Symbios Logic SAS1064ET PCI-Express Fusion-MPT SAS
             +-04.0-[0000:03]--
             +-05.0-[0000:04]--
             +-07.0-[0000:05]--+-00.0  nVidia Corporation GT218 [GeForce G210]
             |                 \-00.1  nVidia Corporation High Definition Audio Controller
             +-0d.0  Intel Corporation Device 343a
 [....snip.....]
             +-0d.1  Intel Corporation Device 343b

#cat /proc/iomem
[....snip....]
3fbf3000-3fffffff : reserved
50000000-7fffffff : PCI Bus 0000:00
  50000000-630fffff : PCI Bus 0000:05
    50000000-5fffffff : 0000:05:00.0
    60000000-61ffffff : 0000:05:00.0
    62000000-62ffffff : 0000:05:00.0
    63000000-63003fff : 0000:05:00.1
      63000000-63003fff : ICH HD audio
  64000000-680fffff : PCI Bus 0000:0a
    64000000-67ffffff : 0000:0a:00.0
    68000000-6803ffff : 0000:0a:00.0
[....snip....]
  68314000-68317fff : 0000:00:16.5
  68318000-6831bfff : 0000:00:16.6
  6831c000-6831ffff : 0000:00:16.7
  68320000-68320fff : 0000:00:13.0
  68321000-683213ff : 0000:00:1d.7
    68321000-683213ff : ehci_hcd
  68321400-683217ff : 0000:00:1a.7
    68321400-683217ff : ehci_hcd
  68321800-683218ff : 0000:00:1f.3
80000000-9fffffff : PCI Bus 0000:40
  80000000-800fffff : PCI Bus 0000:46
    80000000-8001ffff : 0000:46:00.1
      80000000-8001ffff : igb
    80020000-8003ffff : 0000:46:00.1
      80020000-8003ffff : igb
    80040000-8005ffff : 0000:46:00.0
      80040000-8005ffff : igb
    80060000-8007ffff : 0000:46:00.0
      80060000-8007ffff : igb
    80080000-80083fff : 0000:46:00.1
      80080000-80083fff : igb
    80084000-80087fff : 0000:46:00.0
      80084000-80087fff : igb
  80100000-801fffff : PCI Bus 0000:43
    80100000-8010ffff : 0000:43:00.0
      80100000-8010ffff : mpt
    80110000-80113fff : 0000:43:00.0
      80110000-80113fff : mpt
  80200000-802fffff : PCI Bus 0000:42
    80200000-8021ffff : 0000:42:00.1
      80200000-8021ffff : igb
    80220000-8023ffff : 0000:42:00.1
      80220000-8023ffff : igb
    80240000-8025ffff : 0000:42:00.0
      80240000-8025ffff : igb
    80260000-8027ffff : 0000:42:00.0
      80260000-8027ffff : igb
    80280000-80283fff : 0000:42:00.1
      80280000-80283fff : igb
    80284000-80287fff : 0000:42:00.0
      80284000-80287fff : igb
  80300000-80303fff : 0000:40:16.0
  80304000-80307fff : 0000:40:16.1
  80308000-8030bfff : 0000:40:16.2
  8030c000-8030ffff : 0000:40:16.3
  80310000-80313fff : 0000:40:16.4
  80314000-80317fff : 0000:40:16.5
  80318000-8031bfff : 0000:40:16.6
  8031c000-8031ffff : 0000:40:16.7
  80320000-80320fff : 0000:40:13.0
fea00000-fea0001f : pnp 00:06
[....snip......]
20fc000000-20ffffffff : reserved
1fffffc000000-1fffffc33dcf7 : PCI Bus 0000:00 I/O Ports 00000000-00000cf7
1fffffc400000-1fffffe3fffff : PCI Bus 0000:00 I/O Ports 00001000-00008fff
1fffffe400000-1fffffffffffe : PCI Bus 0000:40 I/O Ports 00009000-0000fffe

2. After hot remove pci root bus 0000:40
#cat /proc/iomem
[....snip.....]
50000000-7fffffff : PCI Bus 0000:00
  50000000-630fffff : PCI Bus 0000:05
    50000000-5fffffff : 0000:05:00.0
    60000000-61ffffff : 0000:05:00.0
    62000000-62ffffff : 0000:05:00.0
    63000000-63003fff : 0000:05:00.1
      63000000-63003fff : ICH HD audio
  64000000-680fffff : PCI Bus 0000:0a
    64000000-67ffffff : 0000:0a:00.0
    68000000-6803ffff : 0000:0a:00.0
  68100000-681fffff : PCI Bus 0000:02
    68100000-6810ffff : 0000:02:00.0
      68100000-6810ffff : mpt
    68110000-68113fff : 0000:02:00.0
      68110000-68113fff : mpt
  68200000-682fffff : PCI Bus 0000:01
    68200000-6821ffff : 0000:01:00.1
      68200000-6821ffff : igb
    68220000-6823ffff : 0000:01:00.1
      68220000-6823ffff : igb
    68240000-6825ffff : 0000:01:00.0
      68240000-6825ffff : igb
    68260000-6827ffff : 0000:01:00.0
      68260000-6827ffff : igb
    68280000-68283fff : 0000:01:00.1
      68280000-68283fff : igb
    68284000-68287fff : 0000:01:00.0
      68284000-68287fff : igb
  68300000-68303fff : 0000:00:16.0
  68304000-68307fff : 0000:00:16.1
  68308000-6830bfff : 0000:00:16.2
  6830c000-6830ffff : 0000:00:16.3
  68310000-68313fff : 0000:00:16.4
  68314000-68317fff : 0000:00:16.5
  68318000-6831bfff : 0000:00:16.6
  6831c000-6831ffff : 0000:00:16.7
  68320000-68320fff : 0000:00:13.0
  68321000-683213ff : 0000:00:1d.7
    68321000-683213ff : ehci_hcd
  68321400-683217ff : 0000:00:1a.7
    68321400-683217ff : ehci_hcd
  68321800-683218ff : 0000:00:1f.3
80000000-9fffffff : PCI Bus 0000:40
  80000000-9fffffff : PCI Bus 0000:40 (<-----------------pci root bus 0000:40 resource is not released)
fea00000-fea0001f : pnp 00:06
fed1b000-fed1bfff : pnp 00:06
fed1c000-fed8bffe : pnp 00:06
  fed1f410-fed1f414 : iTCO_wdt
fee00000-feefffff : pnp 00:06
ff000000-ffffffff : pnp 00:06
[.....snip....]
20fa516000-20fbffffff : System RAM
20fc000000-20ffffffff : reserved
1fffffc000000-1fffffc33dcf7 : PCI Bus 0000:00 I/O Ports 00000000-00000cf7
1fffffc400000-1fffffe3fffff : PCI Bus 0000:00 I/O Ports 00001000-00008fff
1fffffe400000-1fffffffffffe : PCI Bus 0000:40 I/O Ports 00009000-0000fffe
  1fffffe400000-1fffffffffffe : PCI Bus 0000:40 I/O Ports 00009000-0000fffe (<--------------io port map resource is not released)

3. hot add pci root bus 0000:40
linux-ha2:~ # echo "\_SB_.NOD1.PCI1 1" > /sys/kernel/debug/acpi/sci_notify
linux-ha2:~ # dmesg
ACPI: ACPI device name is <\_SB_.NOD1.PCI1>, event code is <1>
ACPI: Notify event is queued
ACPI: \_SB_.NOD1.PCI1: Device check notify on _handle_hotplug_event_root
ACPI: PCI Root Bridge [PCI1] (domain 0000 [bus 40-7f])
acpi PNP0A08:02: Requesting ACPI _OSC control (0x1d)
acpi PNP0A08:02: ACPI _OSC control (0x1d) granted
acpi PNP0A08:02: host bridge window [io  0x9000-0xfffe]
acpi PNP0A08:02: host bridge window [mem 0x80000000-0x9fffffff]
PCI host bridge to bus 0000:40
pci_bus 0000:40: root bus resource [bus 40-7f]
[......snip.......]
pc 0000:40:16.5: [8086:342a] type 00 class 0x088000
pci 0000:40:16.5: reg 10: [mem 0x80314000-0x80317fff 64bit]
pci 0000:40:16.6: [8086:342b] type 00 class 0x088000
pci 0000:40:16.6: reg 10: [mem 0x80318000-0x8031bfff 64bit]
pci 0000:40:16.7: [8086:342c] type 00 class 0x088000
pci 0000:40:16.7: reg 10: [mem 0x8031c000-0x8031ffff 64bit]  (------------------------------conflict resource found bellow---------)
pci 0000:40:13.0: address space collision: [mem 0x80320000-0x80320fff] conflicts with PCI Bus 0000:40 [mem 0x80000000-0x9fffffff]  
pci 0000:40:16.0: address space collision: [mem 0x80300000-0x80303fff 64bit] conflicts with PCI Bus 0000:40 [mem 0x80000000-0x9fffffff]
pci 0000:40:16.1: address space collision: [mem 0x80304000-0x80307fff 64bit] conflicts with PCI Bus 0000:40 [mem 0x80000000-0x9fffffff]
pci 0000:40:16.2: address space collision: [mem 0x80308000-0x8030bfff 64bit] conflicts with PCI Bus 0000:40 [mem 0x80000000-0x9fffffff]
pci 0000:40:16.3: address space collision: [mem 0x8030c000-0x8030ffff 64bit] conflicts with PCI Bus 0000:40 [mem 0x80000000-0x9fffffff]
pci 0000:40:16.4: address space collision: [mem 0x80310000-0x80313fff 64bit] conflicts with PCI Bus 0000:40 [mem 0x80000000-0x9fffffff]
pci 0000:40:16.5: address space collision: [mem 0x80314000-0x80317fff 64bit] conflicts with PCI Bus 0000:40 [mem 0x80000000-0x9fffffff]
pci 0000:40:16.6: address space collision: [mem 0x80318000-0x8031bfff 64bit] conflicts with PCI Bus 0000:40 [mem 0x80000000-0x9fffffff]
pci 0000:40:16.7: address space collision: [mem 0x8031c000-0x8031ffff 64bit] conflicts with PCI Bus 0000:40 [mem 0x80000000-0x9fffffff]
pci 0000:40:00.0: PCI bridge to [bus 41]
pci 0000:42:00.0: [8086:10c9] type 00 class 0x020000
pci 0000:40:07.0: res[8]=[mem 0x00100000-0x001fffff] get_res_add_size add_size 200000
[......snip.......]
pci 0000:40:07.0: res[9]=[mem 0x00100000-0x001fffff pref] get_res_add_size add_size 200000
pci 0000:40:03.0: BAR 9: can't assign mem pref (size 0x400000)
pci 0000:40:01.0: BAR 8: can't assign mem (size 0x100000)
pci 0000:40:01.0: BAR 9: can't assign mem pref (size 0x100000)
pci 0000:40:03.0: BAR 8: can't assign mem (size 0x300000)
pci 0000:40:04.0: BAR 8: can't assign mem (size 0x200000)
pci 0000:40:04.0: BAR 9: can't assign mem pref (size 0x200000)
pci 0000:40:05.0: BAR 8: can't assign mem (size 0x200000)
pci 0000:40:05.0: BAR 9: can't assign mem pref (size 0x200000)
pci 0000:40:07.0: BAR 8: can't assign mem (size 0x300000)
pci 0000:40:07.0: BAR 9: can't assign mem pref (size 0x300000)
pci 0000:40:16.0: BAR 0: can't assign mem (size 0x4000)
pci 0000:40:16.1: BAR 0: can't assign mem (size 0x4000)
pci 0000:40:16.2: BAR 0: can't assign mem (size 0x4000)
pci 0000:40:16.3: BAR 0: can't assign mem (size 0x4000)
pci 0000:40:16.4: BAR 0: can't assign mem (size 0x4000)
pci 0000:40:16.5: BAR 0: can't assign mem (size 0x4000)
pci 0000:40:16.6: BAR 0: can't assign mem (size 0x4000)
pci 0000:40:16.7: BAR 0: can't assign mem (size 0x4000)
pci 0000:40:01.0: BAR 7: can't assign io (size 0x1000)
pci 0000:40:03.0: BAR 7: can't assign io (size 0x2000)
pci 0000:40:04.0: BAR 7: can't assign io (size 0x1000)
pci 0000:40:05.0: BAR 7: can't assign io (size 0x1000)
pci 0000:40:07.0: BAR 7: can't assign io (size 0x2000)
pci 0000:40:03.0: BAR 9: can't assign mem pref (size 0x200000)
pci 0000:40:01.0: BAR 8: can't assign mem (size 0x100000)
pci 0000:40:01.0: BAR 9: can't assign mem pref (size 0x100000)
pci 0000:40:03.0: BAR 8: can't assign mem (size 0x100000)
pci 0000:40:07.0: BAR 8: can't assign mem (size 0x100000)
pci 0000:40:07.0: BAR 9: can't assign mem pref (size 0x100000)
pci 0000:40:16.0: BAR 0: can't assign mem (size 0x4000)
pci 0000:40:16.1: BAR 0: can't assign mem (size 0x4000)
pci 0000:40:16.2: BAR 0: can't assign mem (size 0x4000)
pci 0000:40:16.3: BAR 0: can't assign mem (size 0x4000)
pci 0000:40:16.4: BAR 0: can't assign mem (size 0x4000)
pci 0000:40:16.5: BAR 0: can't assign mem (size 0x4000)
pci 0000:40:16.6: BAR 0: can't assign mem (size 0x4000)
pci 0000:40:16.7: BAR 0: can't assign mem (size 0x4000)
pci 0000:40:01.0: BAR 7: can't assign io (size 0x1000)
pci 0000:40:03.0: BAR 7: can't assign io (size 0x2000)
pci 0000:40:04.0: BAR 7: can't assign io (size 0x1000)
pci 0000:40:05.0: BAR 7: can't assign io (size 0x1000)
pci 0000:40:07.0: BAR 7: can't assign io (size 0x2000)
pci 0000:40:05.0: BAR 8: can't assign mem (size 0x200000)
pci 0000:40:05.0: BAR 9: can't assign mem pref (size 0x200000)
pci 0000:40:04.0: BAR 8: can't assign mem (size 0x200000)
pci 0000:40:04.0: BAR 9: can't assign mem pref (size 0x200000)
pci 0000:40:00.0: PCI bridge to [bus 41]
pci 0000:42:00.0: BAR 6: can't assign mem pref (size 0x20000)
pci 0000:42:00.1: BAR 6: can't assign mem pref (size 0x20000)
pci 0000:40:01.0: PCI bridge to [bus 42]
pci 0000:43:00.0: BAR 6: can't assign mem pref (size 0x200000)
pci 0000:40:03.0: PCI bridge to [bus 43]
pci 0000:40:04.0: PCI bridge to [bus 44]
pci 0000:40:05.0: PCI bridge to [bus 45]
pci 0000:46:00.0: BAR 6: can't assign mem pref (size 0x20000)
pci 0000:46:00.1: BAR 6: can't assign mem pref (size 0x20000)
pci 0000:40:07.0: PCI bridge to [bus 46]


Jiang Liu (1):
  PCI/IA64: fix memleak for create pci root bus fail

Yijing Wang (7):
  PCI/IA64: SN: remove sn_pci_window_fixup()
  PCI/IA64: SN: use normal resource instead of pci_window
  PCI/IA64: embed pci hostbridge resources into pci_root_info
  PCI/IA64: Allocate pci_root_info instead of using stack
  PCI/IA64: add host bridge resource release for _CRS path
  PCI/IA64: introduce probe_pci_root_info() to manage  _CRS resource
  PCI: Replace printks with appropriate pr_*()

 arch/ia64/include/asm/pci.h   |   10 +-
 arch/ia64/pci/pci.c           |  236 ++++++++++++++++++++++++++++-------------
 arch/ia64/sn/kernel/io_init.c |  109 +++++--------------
 3 files changed, 192 insertions(+), 163 deletions(-)

[PATCH -v4 1/8] PCI/IA64: SN: remove sn_pci_window_fixup()

[Yijing Wang]

Currently, pcibios_bus_to_resource() and pcibios_resource_to_bus()
functions use pci_host_bridge_window in pci_host_bridge to translate
bus side to/from cpu side addresses. Pci_window in pci_controller
under IA64 is no used again, so it's no need to use sn_pci_window_fixup()
to setup pci_window again, remove it.

Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Cc: John Keller <jpk@sgi.com>
Cc: Jay Lan <jlan@engr.sgi.com>
Cc: Jack Steiner <steiner@sgi.com>
Cc: Mark Maule <maule@sgi.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: linux-ia64@vger.kernel.org
---
 arch/ia64/sn/kernel/io_init.c |   55 +----------------------------------------
 1 files changed, 1 insertions(+), 54 deletions(-)

diff --git a/arch/ia64/sn/kernel/io_init.c b/arch/ia64/sn/kernel/io_init.c
index 238e2c5..b8ff9ea 100644
--- a/arch/ia64/sn/kernel/io_init.c
+++ b/arch/ia64/sn/kernel/io_init.c
@@ -149,48 +149,6 @@ sn_legacy_pci_window_fixup(struct pci_controller *controller,
 }
 
 /*
- * sn_pci_window_fixup() - Create a pci_window for each device resource.
- *			   It will setup pci_windows for use by
- *			   pcibios_bus_to_resource(), pcibios_resource_to_bus(),
- *			   etc.
- */
-static void
-sn_pci_window_fixup(struct pci_dev *dev, unsigned int count,
-		    s64 * pci_addrs)
-{
-	struct pci_controller *controller = PCI_CONTROLLER(dev->bus);
-	unsigned int i;
-	unsigned int idx;
-	unsigned int new_count;
-	struct pci_window *new_window;
-
-	if (count == 0)
-		return;
-	idx = controller->windows;
-	new_count = controller->windows + count;
-	new_window = kcalloc(new_count, sizeof(struct pci_window), GFP_KERNEL);
-	BUG_ON(new_window == NULL);
-	if (controller->window) {
-		memcpy(new_window, controller->window,
-		       sizeof(struct pci_window) * controller->windows);
-		kfree(controller->window);
-	}
-
-	/* Setup a pci_window for each device resource. */
-	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
-		if (pci_addrs[i] == -1)
-			continue;
-
-		new_window[idx].offset = dev->resource[i].start - pci_addrs[i];
-		new_window[idx].resource = dev->resource[i];
-		idx++;
-	}
-
-	controller->windows = new_count;
-	controller->window = new_window;
-}
-
-/*
  * sn_io_slot_fixup() -   We are not running with an ACPI capable PROM,
  *			  and need to convert the pci_dev->resource
  *			  'start' and 'end' addresses to mapped addresses,
@@ -199,9 +157,7 @@ sn_pci_window_fixup(struct pci_dev *dev, unsigned int count,
 void
 sn_io_slot_fixup(struct pci_dev *dev)
 {
-	unsigned int count = 0;
 	int idx;
-	s64 pci_addrs[PCI_ROM_RESOURCE + 1];
 	unsigned long addr, end, size, start;
 	struct pcidev_info *pcidev_info;
 	struct sn_irq_info *sn_irq_info;
@@ -229,7 +185,6 @@ sn_io_slot_fixup(struct pci_dev *dev)
 	for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
 
 		if (!pcidev_info->pdi_pio_mapped_addr[idx]) {
-			pci_addrs[idx] = -1;
 			continue;
 		}
 
@@ -237,11 +192,8 @@ sn_io_slot_fixup(struct pci_dev *dev)
 		end = dev->resource[idx].end;
 		size = end - start;
 		if (size == 0) {
-			pci_addrs[idx] = -1;
 			continue;
 		}
-		pci_addrs[idx] = start;
-		count++;
 		addr = pcidev_info->pdi_pio_mapped_addr[idx];
 		addr = ((addr << 4) >> 4) | __IA64_UNCACHED_OFFSET;
 		dev->resource[idx].start = addr;
@@ -276,12 +228,7 @@ sn_io_slot_fixup(struct pci_dev *dev)
 						 IORESOURCE_ROM_BIOS_COPY;
 		}
 	}
-	/* Create a pci_window in the pci_controller struct for
-	 * each device resource.
-	 */
-	if (count > 0)
-		sn_pci_window_fixup(dev, count, pci_addrs);
-
+
 	sn_pci_fixup_slot(dev, pcidev_info, sn_irq_info);
 }
 
-- 
1.7.1

[PATCH -v4 2/8] PCI/IA64: SN: use normal resource instead of pci_window

[Yijing Wang]

Pci_window in pci_controller will not be used again,
use normal resource instead of pci_window in
sn_legacy_pci_window_fixup(), this patch is to prepare
remove pci_window in IA64.

Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Cc: John Keller <jpk@sgi.com>
Cc: Jay Lan <jlan@engr.sgi.com>
Cc: Jack Steiner <steiner@sgi.com>
Cc: Mark Maule <maule@sgi.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: linux-ia64@vger.kernel.org
---
 arch/ia64/sn/kernel/io_init.c |   56 +++++++++++++++++++----------------------
 1 files changed, 26 insertions(+), 30 deletions(-)

diff --git a/arch/ia64/sn/kernel/io_init.c b/arch/ia64/sn/kernel/io_init.c
index b8ff9ea..d97e2b4 100644
--- a/arch/ia64/sn/kernel/io_init.c
+++ b/arch/ia64/sn/kernel/io_init.c
@@ -118,34 +118,26 @@ static void __init sn_fixup_ionodes(void)
 }
 
 /*
- * sn_pci_legacy_window_fixup - Create PCI controller windows for
+ * sn_pci_legacy_window_fixup - Setup PCI resources for
  *				legacy IO and MEM space. This needs to
  *				be done here, as the PROM does not have
  *				ACPI support defining the root buses
  *				and their resources (_CRS),
  */
 static void
-sn_legacy_pci_window_fixup(struct pci_controller *controller,
-			   u64 legacy_io, u64 legacy_mem)
+sn_legacy_pci_window_fixup(struct resource *res,
+		u64 legacy_io, u64 legacy_mem)
 {
-		controller->window = kcalloc(2, sizeof(struct pci_window),
-					     GFP_KERNEL);
-		BUG_ON(controller->window == NULL);
-		controller->window[0].offset = legacy_io;
-		controller->window[0].resource.name = "legacy_io";
-		controller->window[0].resource.flags = IORESOURCE_IO;
-		controller->window[0].resource.start = legacy_io;
-		controller->window[0].resource.end =
-	    			controller->window[0].resource.start + 0xffff;
-		controller->window[0].resource.parent = &ioport_resource;
-		controller->window[1].offset = legacy_mem;
-		controller->window[1].resource.name = "legacy_mem";
-		controller->window[1].resource.flags = IORESOURCE_MEM;
-		controller->window[1].resource.start = legacy_mem;
-		controller->window[1].resource.end =
-	    	       controller->window[1].resource.start + (1024 * 1024) - 1;
-		controller->window[1].resource.parent = &iomem_resource;
-		controller->windows = 2;
+		res[0].name = "legacy_io";
+		res[0].flags = IORESOURCE_IO;
+		res[0].start = legacy_io;
+		res[0].end = res[0].start + 0xffff;
+		res[0].parent = &ioport_resource;
+		res[1].name = "legacy_mem";
+		res[1].flags = IORESOURCE_MEM;
+		res[1].start = legacy_mem;
+		res[1].end = res[1].start + (1024 * 1024) - 1;
+		res[1].parent = &iomem_resource;
 }
 
 /*
@@ -244,8 +236,8 @@ sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
 	s64 status = 0;
 	struct pci_controller *controller;
 	struct pcibus_bussoft *prom_bussoft_ptr;
+	struct resource *res;
 	LIST_HEAD(resources);
-	int i;
 
  	status = sal_get_pcibus_info((u64) segment, (u64) busnum,
  				     (u64) ia64_tpa(&prom_bussoft_ptr));
@@ -257,19 +249,23 @@ sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
 	BUG_ON(!controller);
 	controller->segment = segment;
 
+	res = kcalloc(2, sizeof(struct resource), GFP_KERNEL);
+	BUG_ON(!res);
+
 	/*
 	 * Temporarily save the prom_bussoft_ptr for use by sn_bus_fixup().
 	 * (platform_data will be overwritten later in sn_common_bus_fixup())
 	 */
 	controller->platform_data = prom_bussoft_ptr;
 
-	sn_legacy_pci_window_fixup(controller,
-				   prom_bussoft_ptr->bs_legacy_io,
-				   prom_bussoft_ptr->bs_legacy_mem);
-	for (i = 0; i < controller->windows; i++)
-		pci_add_resource_offset(&resources,
-					&controller->window[i].resource,
-					controller->window[i].offset);
+	sn_legacy_pci_window_fixup(res,
+			prom_bussoft_ptr->bs_legacy_io,
+			prom_bussoft_ptr->bs_legacy_mem);
+	pci_add_resource_offset(&resources,	&res[0],
+			prom_bussoft_ptr->bs_legacy_io);
+	pci_add_resource_offset(&resources,	&res[1],
+			prom_bussoft_ptr->bs_legacy_mem);
+
 	bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, controller,
 				&resources);
  	if (bus == NULL)
@@ -280,7 +276,7 @@ sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
 	return;
 
 error_return:
-
+	kfree(res);
 	kfree(controller);
 	return;
 }
-- 
1.7.1

[PATCH -v4 3/8] PCI/IA64: embed pci hostbridge resources into pci_root_info

[Yijing Wang]

Currently, pcibios_resource_to_bus() and pcibios_bus_to_resource()
functions use pci_host_bridge to translate bus side address from/to
cpu side address. The pci_window in pci_controller never be used again.
So we remove pci_window in pci_controller and embed hostbridge resource
into pci_root_info. Bjorn suggested to implement hostbridge resources
release in IA64 like in X86, this patch is to prepare for that.

Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: Yinghai Lu <yinghai@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Thierry Reding <thierry.reding@avionic-design.de>
Cc: linux-ia64@vger.kernel.org
---
 arch/ia64/include/asm/pci.h |    9 +-----
 arch/ia64/pci/pci.c         |   65 ++++++++++++++++++++++++------------------
 2 files changed, 38 insertions(+), 36 deletions(-)

diff --git a/arch/ia64/include/asm/pci.h b/arch/ia64/include/asm/pci.h
index 5e04b59..a7ebe5f 100644
--- a/arch/ia64/include/asm/pci.h
+++ b/arch/ia64/include/asm/pci.h
@@ -89,23 +89,16 @@ extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
 #define pci_legacy_read platform_pci_legacy_read
 #define pci_legacy_write platform_pci_legacy_write
 
-struct pci_window {
-	struct resource resource;
-	u64 offset;
-};
-
 struct pci_controller {
 	void *acpi_handle;
 	void *iommu;
 	int segment;
 	int node;		/* nearest node with memory or -1 for global allocation */
 
-	unsigned int windows;
-	struct pci_window *window;
-
 	void *platform_data;
 };
 
+
 #define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
 #define pci_domain_nr(busdev)    (PCI_CONTROLLER(busdev)->segment)
 
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index de1474f..a2f91b0 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -134,6 +134,9 @@ struct pci_root_info {
 	struct acpi_device *bridge;
 	struct pci_controller *controller;
 	struct list_head resources;
+	struct resource *res;
+	resource_size_t *res_offset;
+	unsigned int res_num;
 	char *name;
 };
 
@@ -265,7 +268,7 @@ static acpi_status count_window(struct acpi_resource *resource, void *data)
 static acpi_status add_window(struct acpi_resource *res, void *data)
 {
 	struct pci_root_info *info = data;
-	struct pci_window *window;
+	struct resource *resource;
 	struct acpi_resource_address64 addr;
 	acpi_status status;
 	unsigned long flags, offset = 0;
@@ -289,37 +292,36 @@ static acpi_status add_window(struct acpi_resource *res, void *data)
 	} else
 		return AE_OK;
 
-	window = &info->controller->window[info->controller->windows++];
-	window->resource.name = info->name;
-	window->resource.flags = flags;
-	window->resource.start = addr.minimum + offset;
-	window->resource.end = window->resource.start + addr.address_length - 1;
-	window->offset = offset;
+	resource = &info->res[info->res_num];
+	resource->name = info->name;
+	resource->flags = flags;
+	resource->start = addr.minimum + offset;
+	resource->end = resource->start + addr.address_length - 1;
+	info->res_offset[info->res_num] = offset;
 
-	if (insert_resource(root, &window->resource)) {
+	if (insert_resource(root, resource)) {
 		dev_err(&info->bridge->dev,
 			"can't allocate host bridge window %pR\n",
-			&window->resource);
+			resource);
 	} else {
 		if (offset)
 			dev_info(&info->bridge->dev, "host bridge window %pR "
 				 "(PCI address [%#llx-%#llx])\n",
-				 &window->resource,
-				 window->resource.start - offset,
-				 window->resource.end - offset);
+				 resource,
+				 resource->start - offset,
+				 resource->end - offset);
 		else
 			dev_info(&info->bridge->dev,
-				 "host bridge window %pR\n",
-				 &window->resource);
+				 "host bridge window %pR\n", resource);
 	}
-
 	/* HP's firmware has a hack to work around a Windows bug.
 	 * Ignore these tiny memory ranges */
-	if (!((window->resource.flags & IORESOURCE_MEM) &&
-	      (window->resource.end - window->resource.start < 16)))
-		pci_add_resource_offset(&info->resources, &window->resource,
-					window->offset);
+	if (!((resource->flags & IORESOURCE_MEM) &&
+	      (resource->end - resource->start < 16)))
+		pci_add_resource_offset(&info->resources, resource,
+					info->res_offset[info->res_num]);
 
+	info->res_num++;
 	return AE_OK;
 }
 
@@ -329,7 +331,6 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 	int domain = root->segment;
 	int bus = root->secondary.start;
 	struct pci_controller *controller;
-	unsigned int windows = 0;
 	struct pci_root_info info;
 	struct pci_bus *pbus;
 	char *name;
@@ -351,22 +352,29 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 	/* insert busn resource at first */
 	pci_add_resource(&info.resources, &root->secondary);
 	acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
-			&windows);
-	if (windows) {
-		controller->window =
-			kzalloc_node(sizeof(*controller->window) * windows,
+			&info.res_num);
+	if (info.res_num) {
+		info.res =
+			kzalloc_node(sizeof(*info.res) * info.res_num,
 				     GFP_KERNEL, controller->node);
-		if (!controller->window)
+		if (!info.res)
 			goto out2;
+
+		info.res_offset =
+			kzalloc_node(sizeof(*info.res_offset) * info.res_num,
+				GFP_KERNEL, controller->node);
+		if (!info.res_offset)
+			goto out3;
 
 		name = kmalloc(16, GFP_KERNEL);
 		if (!name)
-			goto out3;
+			goto out4;
 
 		sprintf(name, "PCI Bus %04x:%02x", domain, bus);
 		info.bridge = device;
 		info.controller = controller;
 		info.name = name;
+		info.res_num = 0;
 		acpi_walk_resources(device->handle, METHOD_NAME__CRS,
 			add_window, &info);
 	}
@@ -385,9 +393,10 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 
 	pci_scan_child_bus(pbus);
 	return pbus;
-
+out4:
+	kfree(info.res_offset);
 out3:
-	kfree(controller->window);
+	kfree(info.res);
 out2:
 	kfree(controller);
 out1:
-- 
1.7.1

[PATCH -v4 4/8] PCI/IA64: Allocate pci_root_info instead of using stack

[Yijing Wang]

We need to pass around info for release function.

Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: Yinghai Lu <yinghai@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-ia64@vger.kernel.org
---
 arch/ia64/pci/pci.c |   59 ++++++++++++++++++++++++++++++--------------------
 1 files changed, 35 insertions(+), 24 deletions(-)

diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index a2f91b0..3a8b361 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -331,7 +331,8 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 	int domain = root->segment;
 	int bus = root->secondary.start;
 	struct pci_controller *controller;
-	struct pci_root_info info;
+	struct pci_root_info *info = NULL;
+	int busnum = root->secondary.start;
 	struct pci_bus *pbus;
 	char *name;
 	int pxm;
@@ -348,35 +349,42 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 		controller->node = pxm_to_node(pxm);
 #endif
 
-	INIT_LIST_HEAD(&info.resources);
+	info = kzalloc(sizeof(*info), GFP_KERNEL);
+	if (!info) {
+		printk(KERN_WARNING "pci_bus %04x:%02x: "
+				"ignored (out of memory)\n", root->segment, busnum);
+		goto out2;
+	}
+
+	INIT_LIST_HEAD(&info->resources);
 	/* insert busn resource at first */
-	pci_add_resource(&info.resources, &root->secondary);
+	pci_add_resource(&info->resources, &root->secondary);
 	acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
-			&info.res_num);
-	if (info.res_num) {
-		info.res =
-			kzalloc_node(sizeof(*info.res) * info.res_num,
+			&info->res_num);
+	if (info->res_num) {
+		info->res =
+			kzalloc_node(sizeof(*info->res) * info->res_num,
 				     GFP_KERNEL, controller->node);
-		if (!info.res)
-			goto out2;
-		
-		info.res_offset = 
-			kzalloc_node(sizeof(*info.res_offset) * info.res_num,
-				GFP_KERNEL, controller->node);
-		if (!info.res_offset)
+		if (!info->res)
 			goto out3;
+
+		info->res_offset =
+			kzalloc_node(sizeof(*info->res_offset) * info->res_num,
+					GFP_KERNEL, controller->node);
+		if (!info->res_offset)
+			goto out4;
 
 		name = kmalloc(16, GFP_KERNEL);
 		if (!name)
-			goto out4;
+			goto out5;
 
 		sprintf(name, "PCI Bus %04x:%02x", domain, bus);
-		info.bridge = device;
-		info.controller = controller;
-		info.name = name;
-		info.res_num = 0;
+		info->bridge = device;
+		info->controller = controller;
+		info->name = name;
+		info->res_num = 0;
 		acpi_walk_resources(device->handle, METHOD_NAME__CRS,
-			add_window, &info);
+			add_window, info);
 	}
 	/*
 	 * See arch/x86/pci/acpi.c.
@@ -385,18 +393,21 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 	 * such quirk. So we just ignore the case now.
 	 */
 	pbus = pci_create_root_bus(NULL, bus, &pci_root_ops, controller,
-				   &info.resources);
+				   &info->resources);
 	if (!pbus) {
-		pci_free_resource_list(&info.resources);
+		pci_free_resource_list(&info->resources);
 		return NULL;
 	}
 
 	pci_scan_child_bus(pbus);
 	return pbus;
+
+out5:
+	kfree(info->res_offset);
 out4:
-	kfree(info.res_offset);
+	kfree(info->res);
 out3:
-	kfree(info.res);
+	kfree(info);
 out2:
 	kfree(controller);
 out1:
-- 
1.7.1

[PATCH -v4 5/8] PCI/IA64: fix memleak for create pci root bus fail

[Yijing Wang]

From: Jiang Liu <jiang.liu@huawei.com>

If pci_create_root_bus() return fail, we should release
pci root info, pci controller etc.

Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: Yinghai Lu <yinghai@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-ia64@vger.kernel.org
---
 arch/ia64/include/asm/pci.h |    5 +++
 arch/ia64/pci/pci.c         |   75 ++++++++++++++++++++++++++++++++++--------
 2 files changed, 65 insertions(+), 15 deletions(-)

diff --git a/arch/ia64/include/asm/pci.h b/arch/ia64/include/asm/pci.h
index a7ebe5f..00487b8 100644
--- a/arch/ia64/include/asm/pci.h
+++ b/arch/ia64/include/asm/pci.h
@@ -89,6 +89,11 @@ extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
 #define pci_legacy_read platform_pci_legacy_read
 #define pci_legacy_write platform_pci_legacy_write
 
+struct iospace_resource {
+	struct list_head list;
+	struct resource res;
+};
+
 struct pci_controller {
 	void *acpi_handle;
 	void *iommu;
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index 3a8b361..dfb6149 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -137,6 +137,7 @@ struct pci_root_info {
 	struct resource *res;
 	resource_size_t *res_offset;
 	unsigned int res_num;
+	struct list_head io_resources;
 	char *name;
 };
 
@@ -171,25 +172,21 @@ new_space (u64 phys_base, int sparse)
 static u64 add_io_space(struct pci_root_info *info,
 			struct acpi_resource_address64 *addr)
 {
+	struct iospace_resource *iospace;
 	struct resource *resource;
 	char *name;
 	unsigned long base, min, max, base_port;
 	unsigned int sparse = 0, space_nr, len;
 
-	resource = kzalloc(sizeof(*resource), GFP_KERNEL);
-	if (!resource) {
+	len = strlen(info->name) + 32;
+	iospace = kzalloc(sizeof(*iospace) + len, GFP_KERNEL);
+	if (!iospace) {
 		printk(KERN_ERR "PCI: No memory for %s I/O port space\n",
 			info->name);
 		goto out;
 	}
 
-	len = strlen(info->name) + 32;
-	name = kzalloc(len, GFP_KERNEL);
-	if (!name) {
-		printk(KERN_ERR "PCI: No memory for %s I/O port space name\n",
-			info->name);
-		goto free_resource;
-	}
+	name = (char *)(iospace + 1);
 
 	min = addr->minimum;
 	max = min + addr->address_length - 1;
@@ -198,7 +195,7 @@ static u64 add_io_space(struct pci_root_info *info,
 
 	space_nr = new_space(addr->translation_offset, sparse);
 	if (space_nr == ~0)
-		goto free_name;
+		goto free_resource;
 
 	base = __pa(io_space[space_nr].mmio_base);
 	base_port = IO_SPACE_BASE(space_nr);
@@ -213,18 +210,23 @@ static u64 add_io_space(struct pci_root_info *info,
 	if (space_nr == 0)
 		sparse = 1;
 
+	resource = &iospace->res;
 	resource->name  = name;
 	resource->flags = IORESOURCE_MEM;
 	resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);
 	resource->end   = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);
-	insert_resource(&iomem_resource, resource);
+	if (insert_resource(&iomem_resource, resource)) {
+		dev_err(&info->bridge->dev,
+				"can't allocate host bridge io space resource  %pR\n",
+				resource);
+		goto free_resource;
+	}
 
+	list_add_tail(&iospace->list, &info->io_resources);
 	return base_port;
 
-free_name:
-	kfree(name);
 free_resource:
-	kfree(resource);
+	kfree(iospace);
 out:
 	return ~0;
 }
@@ -325,6 +327,47 @@ static acpi_status add_window(struct acpi_resource *res, void *data)
 	return AE_OK;
 }
 
+static void free_pci_root_info_res(struct pci_root_info *info)
+{
+	struct iospace_resource *iospace, *tmp;
+
+	list_for_each_entry_safe(iospace, tmp, &info->io_resources, list)
+		kfree(iospace);
+
+	kfree(info->res);
+	info->res = NULL;
+	kfree(info->res_offset);
+	info->res_offset = NULL;
+	info->res_num = 0;
+	kfree(info->controller);
+	info->controller = NULL;
+}
+
+static void __release_pci_root_info(struct pci_root_info *info)
+{
+	int i;
+	struct resource *res;
+	struct iospace_resource *iospace;
+
+	list_for_each_entry(iospace, &info->io_resources, list)
+		release_resource(&iospace->res);
+
+	for (i = 0; i < info->res_num; i++) {
+		res = &info->res[i];
+
+		if (!res->parent)
+			continue;
+
+		if (!(res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
+			continue;
+
+		release_resource(res);
+	}
+
+	free_pci_root_info_res(info);
+	kfree(info);
+}
+
 struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 {
 	struct acpi_device *device = root->device;
@@ -355,7 +398,8 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 				"ignored (out of memory)\n", root->segment, busnum);
 		goto out2;
 	}
-
+
+	INIT_LIST_HEAD(&info->io_resources);
 	INIT_LIST_HEAD(&info->resources);
 	/* insert busn resource at first */
 	pci_add_resource(&info->resources, &root->secondary);
@@ -396,6 +440,7 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 				   &info->resources);
 	if (!pbus) {
 		pci_free_resource_list(&info->resources);
+		__release_pci_root_info(info);
 		return NULL;
 	}
 
-- 
1.7.1

[PATCH -v4 6/8] PCI/IA64: add host bridge resource release for _CRS path

[Yijing Wang]

Set IA64 host bridge release function to make sure root bridge
related resources get freed during root bus removal.

Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: Yinghai Lu <yinghai@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-ia64@vger.kernel.org
---
 arch/ia64/pci/pci.c |   11 ++++++++++-
 1 files changed, 10 insertions(+), 1 deletions(-)

diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index dfb6149..4383b03 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -368,6 +368,13 @@ static void __release_pci_root_info(struct pci_root_info *info)
 	kfree(info);
 }
 
+static void release_pci_root_info(struct pci_host_bridge *bridge)
+{
+	struct pci_root_info *info = bridge->release_data;
+
+	__release_pci_root_info(info);
+}
+
 struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 {
 	struct acpi_device *device = root->device;
@@ -443,7 +450,9 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 		__release_pci_root_info(info);
 		return NULL;
 	}
-
+
+	pci_set_host_bridge_release(to_pci_host_bridge(pbus->bridge),
+			release_pci_root_info, info);
 	pci_scan_child_bus(pbus);
 	return pbus;
 
-- 
1.7.1

[PATCH -v4 7/8] PCI/IA64: introduce probe_pci_root_info() to manage _CRS resource

[Yijing Wang]

Currently, initialize _CRS resource code in IA64 make pci_acpi_scan_root()
some lengthiness. Introduce probe_pci_root_info() to manage it like in X86,

Signed-off-by: Yijing Wang <wangyijing@huawei.com>
---
 arch/ia64/pci/pci.c |  100 +++++++++++++++++++++++++++++----------------------
 1 files changed, 57 insertions(+), 43 deletions(-)

diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index 4383b03..f2139b4 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -375,6 +375,50 @@ static void release_pci_root_info(struct pci_host_bridge *bridge)
 	__release_pci_root_info(info);
 }
 
+static int
+probe_pci_root_info(struct pci_root_info *info, struct acpi_device *device,
+		int busnum, int domain)
+{
+	char *name;
+
+	name = kmalloc(16, GFP_KERNEL);
+	if (!name)
+		return -ENOMEM;
+
+	sprintf(name, "PCI Bus %04x:%02x", domain, busnum);
+	info->bridge = device;
+	info->name = name;
+
+	acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
+			&info->res_num);
+	if (info->res_num) {
+		info->res =
+			kzalloc_node(sizeof(*info->res) * info->res_num,
+				     GFP_KERNEL, info->controller->node);
+		if (!info->res) {
+			kfree(name);
+			return -ENOMEM;
+		}
+
+		info->res_offset =
+			kzalloc_node(sizeof(*info->res_offset) * info->res_num,
+					GFP_KERNEL, info->controller->node);
+		if (!info->res_offset) {
+			kfree(name);
+			kfree(info->res);
+			info->res = NULL;
+			return -ENOMEM;
+		}
+
+		info->res_num = 0;
+		acpi_walk_resources(device->handle, METHOD_NAME__CRS,
+			add_window, info);
+	} else
+		kfree(name);
+
+	return 0;
+}
+
 struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 {
 	struct acpi_device *device = root->device;
@@ -384,12 +428,11 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 	struct pci_root_info *info = NULL;
 	int busnum = root->secondary.start;
 	struct pci_bus *pbus;
-	char *name;
-	int pxm;
+	int pxm, ret;
 
 	controller = alloc_pci_controller(domain);
 	if (!controller)
-		goto out1;
+		return NULL;
 
 	controller->acpi_handle = device->handle;
 
@@ -402,41 +445,23 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 	info = kzalloc(sizeof(*info), GFP_KERNEL);
 	if (!info) {
 		printk(KERN_WARNING "pci_bus %04x:%02x: "
-				"ignored (out of memory)\n", root->segment, busnum);
-		goto out2;
+				"ignored (out of memory)\n", domain, busnum);
+		kfree(controller);
+		return NULL;
 	}
 	
+	info->controller = controller;
 	INIT_LIST_HEAD(&info->io_resources);
 	INIT_LIST_HEAD(&info->resources);
+	ret = probe_pci_root_info(info, device, busnum, domain);
+	if (ret) {
+		kfree(info->controller);
+		kfree(info);
+		return NULL;
+	}
+
 	/* insert busn resource at first */
 	pci_add_resource(&info->resources, &root->secondary);
-	acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
-			&info->res_num);
-	if (info->res_num) {
-		info->res =
-			kzalloc_node(sizeof(*info->res) * info->res_num,
-				     GFP_KERNEL, controller->node);
-		if (!info->res)
-			goto out3;
-		
-		info->res_offset = 
-			kzalloc_node(sizeof(*info->res_offset) * info->res_num, 
-					GFP_KERNEL, controller->node);
-		if (!info->res_offset)
-			goto out4;
-
-		name = kmalloc(16, GFP_KERNEL);
-		if (!name)
-			goto out5;
-
-		sprintf(name, "PCI Bus %04x:%02x", domain, bus);
-		info->bridge = device;
-		info->controller = controller;
-		info->name = name;
-		info->res_num = 0;
-		acpi_walk_resources(device->handle, METHOD_NAME__CRS,
-			add_window, info);
-	}
 	/*
 	 * See arch/x86/pci/acpi.c.
 	 * The desired pci bus might already be scanned in a quirk. We
@@ -455,17 +480,6 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 			release_pci_root_info, info);
 	pci_scan_child_bus(pbus);
 	return pbus;
-
-out5:
-	kfree(info->res_offset);
-out4:
-	kfree(info->res);
-out3:
-	kfree(info);
-out2:
-	kfree(controller);
-out1:
-	return NULL;
 }
 
 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
-- 
1.7.1

[PATCH -v4 8/8] PCI: Replace printks with appropriate pr_*()

[Yijing Wang]

Replace deprecated printk(KERN_ERR...) with pr_err() in arch/ia64/pci/pci.c

Signed-off-by: Yijing Wang <wangyijing@huawei.com>
---
 arch/ia64/pci/pci.c |   16 +++++++++-------
 1 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index f2139b4..3d26db3 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -157,7 +157,7 @@ new_space (u64 phys_base, int sparse)
 			return i;
 
 	if (num_io_spaces == MAX_IO_SPACES) {
-		printk(KERN_ERR "PCI: Too many IO port spaces "
+		pr_err("PCI: Too many IO port spaces "
 			"(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES);
 		return ~0;
 	}
@@ -181,8 +181,9 @@ static u64 add_io_space(struct pci_root_info *info,
 	len = strlen(info->name) + 32;
 	iospace = kzalloc(sizeof(*iospace) + len, GFP_KERNEL);
 	if (!iospace) {
-		printk(KERN_ERR "PCI: No memory for %s I/O port space\n",
-			info->name);
+		dev_err(&info->bridge->dev,
+				"PCI: No memory for %s I/O port space\n",
+				info->name);
 		goto out;
 	}
 
@@ -444,8 +445,9 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 
 	info = kzalloc(sizeof(*info), GFP_KERNEL);
 	if (!info) {
-		printk(KERN_WARNING "pci_bus %04x:%02x: "
-				"ignored (out of memory)\n", domain, busnum);
+		dev_err(&device->dev,
+				"pci_bus %04x:%02x: ignored (out of memory)\n",
+				domain, busnum);
 		kfree(controller);
 		return NULL;
 	}
@@ -779,7 +781,7 @@ static void __init set_pci_dfl_cacheline_size(void)
 
 	status = ia64_pal_cache_summary(&levels, &unique_caches);
 	if (status != 0) {
-		printk(KERN_ERR "%s: ia64_pal_cache_summary() failed "
+		pr_err("%s: ia64_pal_cache_summary() failed "
 			"(status=%ld)\n", __func__, status);
 		return;
 	}
@@ -787,7 +789,7 @@ static void __init set_pci_dfl_cacheline_size(void)
 	status = ia64_pal_cache_config_info(levels - 1,
 				/* cache_type (data_or_unified)= */ 2, &cci);
 	if (status != 0) {
-		printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed "
+		pr_err("%s: ia64_pal_cache_config_info() failed "
 			"(status=%ld)\n", __func__, status);
 		return;
 	}
-- 
1.7.1

Re: [PATCH -v4 0/8] Add hostbridge resource release to support root bus hotplug in IA64

[Bjorn Helgaas]

On Wed, Jun 5, 2013 at 12:01 AM, Yijing Wang <wangyijing@huawei.com> wrote:
> v3->v4: fix memory allocation problem and use dev_err instead of pr_err follow Bjorn's suggestion.

What does this series apply to?  I normally apply patches to topic
branches based on -rc1, but these don't apply cleanly to either
v3.10-rc1 or to the next-20130605 linux-next tree.

Bjorn

Re: [PATCH -v4 0/8] Add hostbridge resource release to support root bus hotplug in IA64

[Yijing Wang]

Hi Bjorn,
   This series is based your pci-next branch, I used stgit to format this series, I try to
git am them to pci-next, but indeed patch 4 was applied fail, it's strange.
Now I use git format-patch to format this series again, tag v5, and test them in pci-next, result is ok.

Thanks!
Yijing.

On 2013/6/6 1:27, Bjorn Helgaas wrote:
> On Wed, Jun 5, 2013 at 12:01 AM, Yijing Wang <wangyijing@huawei.com> wrote:
>> v3->v4: fix memory allocation problem and use dev_err instead of pr_err follow Bjorn's suggestion.
> 
> What does this series apply to?  I normally apply patches to topic
> branches based on -rc1, but these don't apply cleanly to either
> v3.10-rc1 or to the next-20130605 linux-next tree.
> 
> Bjorn
> 
> 


-- 
Thanks!
Yijing