* [net-next v2 08/15] PCI: expose pcie_link_speed and pcix_bus_speed arrays
2013-07-31 9:59 [net-next v2 00/15][pull request] Intel Wired LAN Driver Updates Jeff Kirsher
@ 2013-07-31 9:59 ` Jeff Kirsher
2013-07-31 19:56 ` Bjorn Helgaas
2013-07-31 9:59 ` [net-next v2 09/15] PCI: move enum pcie_link_width into pci.h Jeff Kirsher
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: Jeff Kirsher @ 2013-07-31 9:59 UTC (permalink / raw)
To: davem, bhelgaas
Cc: Jacob Keller, netdev, gospo, sassmann, linux-pci, Jeff Kirsher
From: Jacob Keller <jacob.e.keller@intel.com>
pcie_link_speed and pcix_bus_speed are arrays used by probe.c to correctly
convert lnksta register values into the pci_bus_speed enum. These static arrays
are useful outside probe for this purpose. This patch makes these defines into
conist arrays and exposes them with an extern header in drivers/pci/pci.h
-v2-
* move extern declarations to drivers/pci/pci.h
CC: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
drivers/pci/pci.h | 3 +++
drivers/pci/probe.c | 4 ++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index d1182c4..948d1a0 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -6,6 +6,9 @@
#define PCI_CFG_SPACE_SIZE 256
#define PCI_CFG_SPACE_EXP_SIZE 4096
+extern const unsigned char pcix_bus_speed[];
+extern const unsigned char pcie_link_speed[];
+
/* Functions internal to the PCI core code */
int pci_create_sysfs_dev_files(struct pci_dev *pdev);
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 46ada5c..496c5b0 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -513,7 +513,7 @@ static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
return bridge;
}
-static unsigned char pcix_bus_speed[] = {
+const unsigned char pcix_bus_speed[] = {
PCI_SPEED_UNKNOWN, /* 0 */
PCI_SPEED_66MHz_PCIX, /* 1 */
PCI_SPEED_100MHz_PCIX, /* 2 */
@@ -532,7 +532,7 @@ static unsigned char pcix_bus_speed[] = {
PCI_SPEED_133MHz_PCIX_533 /* F */
};
-static unsigned char pcie_link_speed[] = {
+const unsigned char pcie_link_speed[] = {
PCI_SPEED_UNKNOWN, /* 0 */
PCIE_SPEED_2_5GT, /* 1 */
PCIE_SPEED_5_0GT, /* 2 */
--
1.7.11.7
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [net-next v2 08/15] PCI: expose pcie_link_speed and pcix_bus_speed arrays
2013-07-31 9:59 ` [net-next v2 08/15] PCI: expose pcie_link_speed and pcix_bus_speed arrays Jeff Kirsher
@ 2013-07-31 19:56 ` Bjorn Helgaas
0 siblings, 0 replies; 6+ messages in thread
From: Bjorn Helgaas @ 2013-07-31 19:56 UTC (permalink / raw)
To: Jeff Kirsher
Cc: David Miller, Jacob Keller, netdev, gospo@redhat.com,
sassmann@redhat.com, linux-pci@vger.kernel.org
On Wed, Jul 31, 2013 at 3:59 AM, Jeff Kirsher
<jeffrey.t.kirsher@intel.com> wrote:
> From: Jacob Keller <jacob.e.keller@intel.com>
>
> pcie_link_speed and pcix_bus_speed are arrays used by probe.c to correctly
> convert lnksta register values into the pci_bus_speed enum. These static arrays
> are useful outside probe for this purpose. This patch makes these defines into
> conist arrays and exposes them with an extern header in drivers/pci/pci.h
>
> -v2-
> * move extern declarations to drivers/pci/pci.h
>
> CC: Bjorn Helgaas <bhelgaas@google.com>
> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
If you edit this patch to add my ack or for other reasons,
s/conist/const/ above. The "-v2-" text doesn't need to be in the
changelog, so you can omit it completely, or put it after a line
containing only "---". I also conventionally capitalize the first
word of the change summary ("Expose") here; run "git log --oneline
drivers/pci/" to see samples.
But don't respin these patches just for that :)
> ---
> drivers/pci/pci.h | 3 +++
> drivers/pci/probe.c | 4 ++--
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index d1182c4..948d1a0 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -6,6 +6,9 @@
> #define PCI_CFG_SPACE_SIZE 256
> #define PCI_CFG_SPACE_EXP_SIZE 4096
>
> +extern const unsigned char pcix_bus_speed[];
> +extern const unsigned char pcie_link_speed[];
> +
> /* Functions internal to the PCI core code */
>
> int pci_create_sysfs_dev_files(struct pci_dev *pdev);
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 46ada5c..496c5b0 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -513,7 +513,7 @@ static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
> return bridge;
> }
>
> -static unsigned char pcix_bus_speed[] = {
> +const unsigned char pcix_bus_speed[] = {
> PCI_SPEED_UNKNOWN, /* 0 */
> PCI_SPEED_66MHz_PCIX, /* 1 */
> PCI_SPEED_100MHz_PCIX, /* 2 */
> @@ -532,7 +532,7 @@ static unsigned char pcix_bus_speed[] = {
> PCI_SPEED_133MHz_PCIX_533 /* F */
> };
>
> -static unsigned char pcie_link_speed[] = {
> +const unsigned char pcie_link_speed[] = {
> PCI_SPEED_UNKNOWN, /* 0 */
> PCIE_SPEED_2_5GT, /* 1 */
> PCIE_SPEED_5_0GT, /* 2 */
> --
> 1.7.11.7
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [net-next v2 09/15] PCI: move enum pcie_link_width into pci.h
2013-07-31 9:59 [net-next v2 00/15][pull request] Intel Wired LAN Driver Updates Jeff Kirsher
2013-07-31 9:59 ` [net-next v2 08/15] PCI: expose pcie_link_speed and pcix_bus_speed arrays Jeff Kirsher
@ 2013-07-31 9:59 ` Jeff Kirsher
2013-07-31 9:59 ` [net-next v2 10/15] PCI: Add function to obtain minimum link width and speed Jeff Kirsher
2013-07-31 20:38 ` [net-next v2 00/15][pull request] Intel Wired LAN Driver Updates David Miller
3 siblings, 0 replies; 6+ messages in thread
From: Jeff Kirsher @ 2013-07-31 9:59 UTC (permalink / raw)
To: davem, bhelgaas
Cc: Jacob Keller, netdev, gospo, sassmann, linux-pci, Jeff Kirsher
From: Jacob Keller <jacob.e.keller@intel.com>
pcie_link_width is the enum used to define the link width values for a pcie
device. This enum should not be contained solely in pci_hotplug.h, and this
patch moves it next to pci_bus_speed in pci.h
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
include/linux/pci.h | 13 +++++++++++++
include/linux/pci_hotplug.h | 13 -------------
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 0fd1f15..a0bf22d 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -183,6 +183,19 @@ enum pci_bus_flags {
PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
};
+/* These values come from the PCI Express Spec */
+enum pcie_link_width {
+ PCIE_LNK_WIDTH_RESRV = 0x00,
+ PCIE_LNK_X1 = 0x01,
+ PCIE_LNK_X2 = 0x02,
+ PCIE_LNK_X4 = 0x04,
+ PCIE_LNK_X8 = 0x08,
+ PCIE_LNK_X12 = 0x0C,
+ PCIE_LNK_X16 = 0x10,
+ PCIE_LNK_X32 = 0x20,
+ PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
+};
+
/* Based on the PCI Hotplug Spec, but some values are made up by us */
enum pci_bus_speed {
PCI_SPEED_33MHz = 0x00,
diff --git a/include/linux/pci_hotplug.h b/include/linux/pci_hotplug.h
index 8db71dc..64e61e0 100644
--- a/include/linux/pci_hotplug.h
+++ b/include/linux/pci_hotplug.h
@@ -28,19 +28,6 @@
#ifndef _PCI_HOTPLUG_H
#define _PCI_HOTPLUG_H
-/* These values come from the PCI Express Spec */
-enum pcie_link_width {
- PCIE_LNK_WIDTH_RESRV = 0x00,
- PCIE_LNK_X1 = 0x01,
- PCIE_LNK_X2 = 0x02,
- PCIE_LNK_X4 = 0x04,
- PCIE_LNK_X8 = 0x08,
- PCIE_LNK_X12 = 0x0C,
- PCIE_LNK_X16 = 0x10,
- PCIE_LNK_X32 = 0x20,
- PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
-};
-
/**
* struct hotplug_slot_ops -the callbacks that the hotplug pci core can use
* @owner: The module owner of this structure
--
1.7.11.7
^ permalink raw reply related [flat|nested] 6+ messages in thread* [net-next v2 10/15] PCI: Add function to obtain minimum link width and speed
2013-07-31 9:59 [net-next v2 00/15][pull request] Intel Wired LAN Driver Updates Jeff Kirsher
2013-07-31 9:59 ` [net-next v2 08/15] PCI: expose pcie_link_speed and pcix_bus_speed arrays Jeff Kirsher
2013-07-31 9:59 ` [net-next v2 09/15] PCI: move enum pcie_link_width into pci.h Jeff Kirsher
@ 2013-07-31 9:59 ` Jeff Kirsher
2013-07-31 20:38 ` [net-next v2 00/15][pull request] Intel Wired LAN Driver Updates David Miller
3 siblings, 0 replies; 6+ messages in thread
From: Jeff Kirsher @ 2013-07-31 9:59 UTC (permalink / raw)
To: davem, bhelgaas
Cc: Jacob Keller, netdev, gospo, sassmann, linux-pci, Jeff Kirsher
From: Jacob Keller <jacob.e.keller@intel.com>
A PCI Express device can potentially report a link width and speed which it will
not properly fulfill due to being plugged into a slower link higher in the
chain. This function walks up the PCI bus chain and calculates the minimum link
width and speed of this entire chain. This can be useful to enable a device to
determine if it has enough bandwidth for optimum functionality.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
drivers/pci/pci.c | 43 +++++++++++++++++++++++++++++++++++++++++++
include/linux/pci.h | 2 ++
2 files changed, 45 insertions(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index e37fea6..c71e78c 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -3579,6 +3579,49 @@ int pcie_set_mps(struct pci_dev *dev, int mps)
}
/**
+ * pcie_get_minimum_link - determine minimum link settings of a PCI device
+ * @dev: PCI device to query
+ * @speed: storage for minimum speed
+ * @width: storage for minimum width
+ *
+ * This function will walk up the PCI device chain and determine the minimum
+ * link width and speed of the device.
+ */
+int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
+ enum pcie_link_width *width)
+{
+ int ret;
+
+ *speed = PCI_SPEED_UNKNOWN;
+ *width = PCIE_LNK_WIDTH_UNKNOWN;
+
+ while (dev) {
+ u16 lnksta;
+ enum pci_bus_speed next_speed;
+ enum pcie_link_width next_width;
+
+ ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
+ if (ret)
+ return ret;
+
+ next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
+ next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
+ PCI_EXP_LNKSTA_NLW_SHIFT;
+
+ if (next_speed < *speed)
+ *speed = next_speed;
+
+ if (next_width < *width)
+ *width = next_width;
+
+ dev = dev->bus->self;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(pcie_get_minimum_link);
+
+/**
* pci_select_bars - Make BAR mask from the type of resource
* @dev: the PCI device for which BAR mask is made
* @flags: resource type mask to be selected
diff --git a/include/linux/pci.h b/include/linux/pci.h
index a0bf22d..2edbee6 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -934,6 +934,8 @@ int pcie_get_readrq(struct pci_dev *dev);
int pcie_set_readrq(struct pci_dev *dev, int rq);
int pcie_get_mps(struct pci_dev *dev);
int pcie_set_mps(struct pci_dev *dev, int mps);
+int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
+ enum pcie_link_width *width);
int __pci_reset_function(struct pci_dev *dev);
int __pci_reset_function_locked(struct pci_dev *dev);
int pci_reset_function(struct pci_dev *dev);
--
1.7.11.7
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [net-next v2 00/15][pull request] Intel Wired LAN Driver Updates
2013-07-31 9:59 [net-next v2 00/15][pull request] Intel Wired LAN Driver Updates Jeff Kirsher
` (2 preceding siblings ...)
2013-07-31 9:59 ` [net-next v2 10/15] PCI: Add function to obtain minimum link width and speed Jeff Kirsher
@ 2013-07-31 20:38 ` David Miller
3 siblings, 0 replies; 6+ messages in thread
From: David Miller @ 2013-07-31 20:38 UTC (permalink / raw)
To: jeffrey.t.kirsher; +Cc: bhelgaas, netdev, gospo, sassmann, linux-pci
From: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Date: Wed, 31 Jul 2013 02:59:22 -0700
> This series contains updates to ixgbe and pci.
...
> git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next master
Looks good, pulled, thanks Jeff.
^ permalink raw reply [flat|nested] 6+ messages in thread