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From: Sean Cross <xobs@kosagi.com>
To: devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Cc: Sascha Hauer <s.hauer@pengutronix.de>,
	Zhu Richard-R65037 <r65037@freescale.com>,
	Shawn Guo <shawn.guo@linaro.org>,
	tharvey@gateworks.com, bhelgaas@google.com,
	Sean Cross <xobs@kosagi.com>
Subject: [PATCH v6 1/3] ARM: imx: Add LVDS general-purpose clocks to i.MX6Q
Date: Mon, 16 Sep 2013 08:20:52 +0000	[thread overview]
Message-ID: <1379319655-20210-2-git-send-email-xobs@kosagi.com> (raw)
In-Reply-To: <1379319655-20210-1-git-send-email-xobs@kosagi.com>

The i.MX6 has two general-purpose LVDS clocks that can be driven
from a variety of sources.  This patch adds a mux and a gate for
both of these clocks.

Signed-off-by: Sean Cross <xobs@kosagi.com>
---
 .../devicetree/bindings/clock/imx6q-clock.txt      |    4 ++++
 arch/arm/mach-imx/clk-imx6q.c                      |   20 +++++++++++++++++++-
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 5a90a72..35e82c7 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -215,6 +215,10 @@ clocks and IDs.
 	cko2      		200
 	cko      		201
 	vdoa      		202
+	lvds1_sel		203
+	lvds2_sel		204
+	lvds1_gate		205
+	lvds2_gate		206
 
 Examples:
 
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 9181a24..d94be84 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -217,6 +217,11 @@ static const char *cko2_sels[] = {
 	"uart_serial", "spdif", "asrc", "hsi_tx",
 };
 static const char *cko_sels[] = { "cko1", "cko2", };
+static const char *lvds_sels[] = {
+	"dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
+	"pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
+	"pcie_ref", "sata_ref",
+};
 
 enum mx6q_clks {
 	dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
@@ -251,7 +256,8 @@ enum mx6q_clks {
 	ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
 	sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
 	usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
-	spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, clk_max
+	spdif, cko2_sel, cko2_podf, cko2, cko, vdoa,
+	lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max
 };
 
 static struct clk *clk[clk_max];
@@ -342,6 +348,18 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 			base + 0xe0, 0, 2, 0, clk_enet_ref_table,
 			&imx_ccm_lock);
 
+	clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
+	clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
+
+	/*
+	 * lvds1_gate and lvds2_gate are pseudo-gates.  Both can be
+	 * independently configured as clock inputs or outputs.  We treat
+	 * the "output_enable" bit as a gate, even though it's really just
+	 * enabling clock output.
+	 */
+	clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10);
+	clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11);
+
 	/*                                name              parent_name        reg       idx */
 	clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
 	clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);
-- 
1.7.9.5


  reply	other threads:[~2013-09-16  8:37 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-09-16  8:20 [PATCH v6 0/3] Add PCIe support for i.MX6q Sean Cross
2013-09-16  8:20 ` Sean Cross [this message]
2013-09-16  8:20 ` [PATCH v6 2/3] ARM: imx6q: Add PCIe bits to GPR syscon definition Sean Cross
2013-09-16  8:20 ` [PATCH v6 3/3] PCI: imx6: Add support for i.MX6 PCIe controller Sean Cross
2013-09-16  9:25   ` Sascha Hauer
2013-09-25 16:05   ` Frank Li
2013-09-26  5:54   ` Tim Harvey
2013-09-27  1:38     ` Zhu Richard-R65037
2013-09-27  2:19       ` Shawn Guo
2013-09-27  3:40         ` Jingoo Han
2013-09-27  3:54           ` Sean Cross
2013-09-27  3:52         ` Tim Harvey
2013-10-18  5:32   ` Tim Harvey
2013-10-18  6:34     ` Zhu Richard-R65037
2013-10-18  7:27       ` Tim Harvey
2013-10-18  7:45         ` Zhu Richard-R65037
2013-10-18 15:34           ` Tim Harvey
2013-11-05 17:35             ` Sinan Akman
2013-11-05 20:28               ` Bjorn Helgaas
2013-09-16  9:11 ` [PATCH v6 0/3] Add PCIe support for i.MX6q Shawn Guo

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