From: Sean Cross <xobs@kosagi.com>
To: devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: Sascha Hauer <s.hauer@pengutronix.de>,
Zhu Richard-R65037 <r65037@freescale.com>,
Shawn Guo <shawn.guo@linaro.org>,
tharvey@gateworks.com, bhelgaas@google.com,
Sean Cross <xobs@kosagi.com>
Subject: [PATCH v6 2/3] ARM: imx6q: Add PCIe bits to GPR syscon definition
Date: Mon, 16 Sep 2013 08:20:53 +0000 [thread overview]
Message-ID: <1379319655-20210-3-git-send-email-xobs@kosagi.com> (raw)
In-Reply-To: <1379319655-20210-1-git-send-email-xobs@kosagi.com>
PCIe requires additional bits be defined for GPR8 and GPR12.
Signed-off-by: Sean Cross <xobs@kosagi.com>
---
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index b6bdcd6..e00e9f3 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -241,6 +241,12 @@
#define IMX6Q_GPR5_L2_CLK_STOP BIT(8)
+#define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25)
+#define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18)
+#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12)
+#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3f << 6)
+#define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3f << 0)
+
#define IMX6Q_GPR9_TZASC2_BYP BIT(1)
#define IMX6Q_GPR9_TZASC1_BYP BIT(0)
@@ -273,7 +279,9 @@
#define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26)
#define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25)
#define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24)
+#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12)
#define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
+#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4)
#define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
--
1.7.9.5
next prev parent reply other threads:[~2013-09-16 8:37 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-16 8:20 [PATCH v6 0/3] Add PCIe support for i.MX6q Sean Cross
2013-09-16 8:20 ` [PATCH v6 1/3] ARM: imx: Add LVDS general-purpose clocks to i.MX6Q Sean Cross
2013-09-16 8:20 ` Sean Cross [this message]
2013-09-16 8:20 ` [PATCH v6 3/3] PCI: imx6: Add support for i.MX6 PCIe controller Sean Cross
2013-09-16 9:25 ` Sascha Hauer
2013-09-25 16:05 ` Frank Li
2013-09-26 5:54 ` Tim Harvey
2013-09-27 1:38 ` Zhu Richard-R65037
2013-09-27 2:19 ` Shawn Guo
2013-09-27 3:40 ` Jingoo Han
2013-09-27 3:54 ` Sean Cross
2013-09-27 3:52 ` Tim Harvey
2013-10-18 5:32 ` Tim Harvey
2013-10-18 6:34 ` Zhu Richard-R65037
2013-10-18 7:27 ` Tim Harvey
2013-10-18 7:45 ` Zhu Richard-R65037
2013-10-18 15:34 ` Tim Harvey
2013-11-05 17:35 ` Sinan Akman
2013-11-05 20:28 ` Bjorn Helgaas
2013-09-16 9:11 ` [PATCH v6 0/3] Add PCIe support for i.MX6q Shawn Guo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1379319655-20210-3-git-send-email-xobs@kosagi.com \
--to=xobs@kosagi.com \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-pci@vger.kernel.org \
--cc=r65037@freescale.com \
--cc=s.hauer@pengutronix.de \
--cc=shawn.guo@linaro.org \
--cc=tharvey@gateworks.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).