From: Mohit Kumar <mohit.kumar@st.com>
To: <jg1.han@samsung.com>
Cc: Mohit Kumar <mohit.kumar@st.com>,
Bjorn Helgaas <bhelgass@google.com>, <spear-devel@list.st.com>,
<linux-pci@vger.kernel.org>
Subject: [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes
Date: Thu, 20 Feb 2014 10:52:53 +0530 [thread overview]
Message-ID: <1392873774-22249-1-git-send-email-mohit.kumar@st.com> (raw)
Corrects comment for setting number of lanes.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Bjorn Helgaas <bhelgass@google.com>
Cc: spear-devel@list.st.com
Cc: linux-pci@vger.kernel.org
---
drivers/pci/host/pcie-designware.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 6d23d8c..391966f 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -766,7 +766,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
u32 membase;
u32 memlimit;
- /* set the number of lines as 4 */
+ /* set the number of lanes */
dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
val &= ~PORT_LINK_MODE_MASK;
switch (pp->lanes) {
--
1.7.0.1
next reply other threads:[~2014-02-20 5:23 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-20 5:22 Mohit Kumar [this message]
2014-02-20 5:22 ` [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport Mohit Kumar
2014-02-20 6:45 ` Mohit KUMAR DCG
2014-02-20 11:38 ` Kishon Vijay Abraham I
2014-02-20 11:58 ` Mohit KUMAR DCG
2014-02-20 12:13 ` Kishon Vijay Abraham I
2014-02-20 13:33 ` Mohit KUMAR DCG
2014-02-21 3:54 ` Pratyush Anand
2014-02-20 6:56 ` [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes Rajeev kumar
2014-02-20 8:29 ` Mohit KUMAR DCG
-- strict thread matches above, loose matches on Subject: below --
2014-02-21 0:59 Jingoo Han
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