* [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes
@ 2014-02-20 5:22 Mohit Kumar
2014-02-20 5:22 ` [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport Mohit Kumar
2014-02-20 6:56 ` [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes Rajeev kumar
0 siblings, 2 replies; 11+ messages in thread
From: Mohit Kumar @ 2014-02-20 5:22 UTC (permalink / raw)
To: jg1.han; +Cc: Mohit Kumar, Bjorn Helgaas, spear-devel, linux-pci
Corrects comment for setting number of lanes.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Bjorn Helgaas <bhelgass@google.com>
Cc: spear-devel@list.st.com
Cc: linux-pci@vger.kernel.org
---
drivers/pci/host/pcie-designware.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 6d23d8c..391966f 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -766,7 +766,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
u32 membase;
u32 memlimit;
- /* set the number of lines as 4 */
+ /* set the number of lanes */
dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
val &= ~PORT_LINK_MODE_MASK;
switch (pp->lanes) {
--
1.7.0.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport
2014-02-20 5:22 [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes Mohit Kumar
@ 2014-02-20 5:22 ` Mohit Kumar
2014-02-20 6:45 ` Mohit KUMAR DCG
2014-02-20 11:38 ` Kishon Vijay Abraham I
2014-02-20 6:56 ` [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes Rajeev kumar
1 sibling, 2 replies; 11+ messages in thread
From: Mohit Kumar @ 2014-02-20 5:22 UTC (permalink / raw)
To: jg1.han; +Cc: Mohit Kumar, Ajay Khandelwal, Bjorn Helgaas, spear-devel,
linux-pci
This patch correct iATU programming for cfg1, io and mem viewport.
Enable ATU only after configuring it.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Ajay Khandelwal <ajay.khandelwal@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Bjorn Helgaas <bhelgass@google.com>
Cc: spear-devel@list.st.com
Cc: linux-pci@vger.kernel.org
---
drivers/pci/host/pcie-designware.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 391966f..46f4a19 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -522,13 +522,13 @@ static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
PCIE_ATU_VIEWPORT);
dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
- dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
PCIE_ATU_LIMIT);
dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
+ dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
}
static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
@@ -537,7 +537,6 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
PCIE_ATU_VIEWPORT);
dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
- dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
@@ -545,6 +544,7 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
PCIE_ATU_UPPER_TARGET);
+ dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
}
static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
@@ -553,7 +553,6 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
PCIE_ATU_VIEWPORT);
dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
- dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
@@ -561,6 +560,7 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
PCIE_ATU_UPPER_TARGET);
+ dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
}
static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
--
1.7.0.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* RE: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport
2014-02-20 5:22 ` [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport Mohit Kumar
@ 2014-02-20 6:45 ` Mohit KUMAR DCG
2014-02-20 11:38 ` Kishon Vijay Abraham I
1 sibling, 0 replies; 11+ messages in thread
From: Mohit KUMAR DCG @ 2014-02-20 6:45 UTC (permalink / raw)
To: jg1.han@samsung.com
Cc: Ajay KHANDELWAL, Bjorn Helgaas, spear-devel,
linux-pci@vger.kernel.org, stable@vger.kerne.org
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes
2014-02-20 5:22 [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes Mohit Kumar
2014-02-20 5:22 ` [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport Mohit Kumar
@ 2014-02-20 6:56 ` Rajeev kumar
2014-02-20 8:29 ` Mohit KUMAR DCG
1 sibling, 1 reply; 11+ messages in thread
From: Rajeev kumar @ 2014-02-20 6:56 UTC (permalink / raw)
To: Mohit KUMAR
Cc: jg1.han@samsung.com, Bjorn Helgaas, spear-devel,
linux-pci@vger.kernel.org
subject line
PCI: designware: Fix comment for setting number of lanes
~Rajeev
On 2/20/2014 10:52 AM, Mohit KUMAR wrote:
> Corrects comment for setting number of lanes.
>
> Signed-off-by: Mohit Kumar<mohit.kumar@st.com>
> Cc: Jingoo Han<jg1.han@samsung.com>
> Cc: Bjorn Helgaas<bhelgass@google.com>
> Cc: spear-devel@list.st.com
> Cc: linux-pci@vger.kernel.org
> ---
> drivers/pci/host/pcie-designware.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 6d23d8c..391966f 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -766,7 +766,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> u32 membase;
> u32 memlimit;
>
> - /* set the number of lines as 4 */
> + /* set the number of lanes */
> dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL,&val);
> val&= ~PORT_LINK_MODE_MASK;
> switch (pp->lanes) {
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes
2014-02-20 6:56 ` [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes Rajeev kumar
@ 2014-02-20 8:29 ` Mohit KUMAR DCG
0 siblings, 0 replies; 11+ messages in thread
From: Mohit KUMAR DCG @ 2014-02-20 8:29 UTC (permalink / raw)
To: Rajeev KUMAR
Cc: jg1.han@samsung.com, Bjorn Helgaas, spear-devel,
linux-pci@vger.kernel.org
SGVsbG8gUmFqZWV2LA0KDQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IFJh
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport
2014-02-20 5:22 ` [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport Mohit Kumar
2014-02-20 6:45 ` Mohit KUMAR DCG
@ 2014-02-20 11:38 ` Kishon Vijay Abraham I
2014-02-20 11:58 ` Mohit KUMAR DCG
1 sibling, 1 reply; 11+ messages in thread
From: Kishon Vijay Abraham I @ 2014-02-20 11:38 UTC (permalink / raw)
To: Mohit Kumar, jg1.han
Cc: Ajay Khandelwal, Bjorn Helgaas, spear-devel, linux-pci
Hi,
On Thursday 20 February 2014 10:52 AM, Mohit Kumar wrote:
> This patch correct iATU programming for cfg1, io and mem viewport.
> Enable ATU only after configuring it.
Does this patch actually fixes device enumeration behind a PCIe-pci bridge or
this is more of cleaning up the sequence?
Thanks
Kishon
>
> Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
> Signed-off-by: Ajay Khandelwal <ajay.khandelwal@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
> Cc: Bjorn Helgaas <bhelgass@google.com>
> Cc: spear-devel@list.st.com
> Cc: linux-pci@vger.kernel.org
> ---
> drivers/pci/host/pcie-designware.c | 6 +++---
> 1 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 391966f..46f4a19 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -522,13 +522,13 @@ static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
> dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
> PCIE_ATU_VIEWPORT);
> dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
> - dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
> dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
> dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
> dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
> PCIE_ATU_LIMIT);
> dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
> dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
> + dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
> }
>
> static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
> @@ -537,7 +537,6 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
> dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
> PCIE_ATU_VIEWPORT);
> dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
> - dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
> dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
> dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
> dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
> @@ -545,6 +544,7 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
> dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
> dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
> PCIE_ATU_UPPER_TARGET);
> + dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
> }
>
> static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
> @@ -553,7 +553,6 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
> dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
> PCIE_ATU_VIEWPORT);
> dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
> - dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
> dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
> dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
> dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
> @@ -561,6 +560,7 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
> dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
> dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
> PCIE_ATU_UPPER_TARGET);
> + dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
> }
>
> static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport
2014-02-20 11:38 ` Kishon Vijay Abraham I
@ 2014-02-20 11:58 ` Mohit KUMAR DCG
2014-02-20 12:13 ` Kishon Vijay Abraham I
0 siblings, 1 reply; 11+ messages in thread
From: Mohit KUMAR DCG @ 2014-02-20 11:58 UTC (permalink / raw)
To: Kishon Vijay Abraham I, jg1.han@samsung.com
Cc: Ajay KHANDELWAL, Bjorn Helgaas, spear-devel,
linux-pci@vger.kernel.org
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport
2014-02-20 11:58 ` Mohit KUMAR DCG
@ 2014-02-20 12:13 ` Kishon Vijay Abraham I
2014-02-20 13:33 ` Mohit KUMAR DCG
2014-02-21 3:54 ` Pratyush Anand
0 siblings, 2 replies; 11+ messages in thread
From: Kishon Vijay Abraham I @ 2014-02-20 12:13 UTC (permalink / raw)
To: Mohit KUMAR DCG, jg1.han@samsung.com
Cc: Ajay KHANDELWAL, Bjorn Helgaas, spear-devel,
linux-pci@vger.kernel.org
Hi Mohit,
On Thursday 20 February 2014 05:28 PM, Mohit KUMAR DCG wrote:
> Hello Kishon,
>
>> -----Original Message-----
>> From: Kishon Vijay Abraham I [mailto:kishon@ti.com]
>> Sent: Thursday, February 20, 2014 5:08 PM
>> To: Mohit KUMAR DCG; jg1.han@samsung.com
>> Cc: Ajay KHANDELWAL; Bjorn Helgaas; spear-devel; linux-
>> pci@vger.kernel.org
>> Subject: Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io
>> and mem viewport
>>
>> Hi,
>>
>> On Thursday 20 February 2014 10:52 AM, Mohit Kumar wrote:
>>> This patch correct iATU programming for cfg1, io and mem viewport.
>>> Enable ATU only after configuring it.
>>
>> Does this patch actually fixes device enumeration behind a PCIe-pci bridge or
>> this is more of cleaning up the sequence?
>>
> - This patch corrects ATU programming sequence. I am not aware of any such issue with
> current driver. Pls specify which bridge do you use in your setup and what is the problem?
I tried with card [1], it had a PLX bridge chip. It couldn't read the
configuration space of the device connected to the PCIe-PCI bridge.
Thanks
Kishon
[1] -> http://ratetorate.in/products/Wiretech-PCIe%252dto%252dPCI-Bridge-Card.
>
> Regards
> Mohit
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport
2014-02-20 12:13 ` Kishon Vijay Abraham I
@ 2014-02-20 13:33 ` Mohit KUMAR DCG
2014-02-21 3:54 ` Pratyush Anand
1 sibling, 0 replies; 11+ messages in thread
From: Mohit KUMAR DCG @ 2014-02-20 13:33 UTC (permalink / raw)
To: Kishon Vijay Abraham I, jg1.han@samsung.com
Cc: Ajay KHANDELWAL, Bjorn Helgaas, spear-devel,
linux-pci@vger.kernel.org
SGVsbG8gS2lzaG9uLA0KDQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IEtp
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes
@ 2014-02-21 0:59 Jingoo Han
0 siblings, 0 replies; 11+ messages in thread
From: Jingoo Han @ 2014-02-21 0:59 UTC (permalink / raw)
To: Mohit Kumar
Cc: Bjorn Helgaas, spear-devel@list.st.com, linux-pci@vger.kernel.org,
Jingoo Han
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport
2014-02-20 12:13 ` Kishon Vijay Abraham I
2014-02-20 13:33 ` Mohit KUMAR DCG
@ 2014-02-21 3:54 ` Pratyush Anand
1 sibling, 0 replies; 11+ messages in thread
From: Pratyush Anand @ 2014-02-21 3:54 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Mohit KUMAR DCG, jg1.han@samsung.com, Ajay KHANDELWAL,
Bjorn Helgaas, spear-devel, linux-pci@vger.kernel.org
On Thu, Feb 20, 2014 at 08:13:08PM +0800, Kishon Vijay Abraham I wrote:
> Hi Mohit,
>
> On Thursday 20 February 2014 05:28 PM, Mohit KUMAR DCG wrote:
> > Hello Kishon,
> >
> >> -----Original Message-----
> >> From: Kishon Vijay Abraham I [mailto:kishon@ti.com]
> >> Sent: Thursday, February 20, 2014 5:08 PM
> >> To: Mohit KUMAR DCG; jg1.han@samsung.com
> >> Cc: Ajay KHANDELWAL; Bjorn Helgaas; spear-devel; linux-
> >> pci@vger.kernel.org
> >> Subject: Re: [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io
> >> and mem viewport
> >>
> >> Hi,
> >>
> >> On Thursday 20 February 2014 10:52 AM, Mohit Kumar wrote:
> >>> This patch correct iATU programming for cfg1, io and mem viewport.
> >>> Enable ATU only after configuring it.
> >>
> >> Does this patch actually fixes device enumeration behind a PCIe-pci bridge or
> >> this is more of cleaning up the sequence?
> >>
> > - This patch corrects ATU programming sequence. I am not aware of any such issue with
> > current driver. Pls specify which bridge do you use in your setup and what is the problem?
>
> I tried with card [1], it had a PLX bridge chip. It couldn't read the
> configuration space of the device connected to the PCIe-PCI bridge.
So do you see abort while reading config space of device connected to
the PCIe-PCI bridge?
Do you see "received master abort" bit set in your RC's cfg register
after you try to read?
Regards
Pratyush
>
> Thanks
> Kishon
>
> [1] -> http://ratetorate.in/products/Wiretech-PCIe%252dto%252dPCI-Bridge-Card.
>
> >
> > Regards
> > Mohit
> >
>
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2014-02-21 3:54 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-02-20 5:22 [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes Mohit Kumar
2014-02-20 5:22 ` [PATCH 2/2] PCI:designware:Fix iATU programming for cfg1, io and mem viewport Mohit Kumar
2014-02-20 6:45 ` Mohit KUMAR DCG
2014-02-20 11:38 ` Kishon Vijay Abraham I
2014-02-20 11:58 ` Mohit KUMAR DCG
2014-02-20 12:13 ` Kishon Vijay Abraham I
2014-02-20 13:33 ` Mohit KUMAR DCG
2014-02-21 3:54 ` Pratyush Anand
2014-02-20 6:56 ` [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes Rajeev kumar
2014-02-20 8:29 ` Mohit KUMAR DCG
-- strict thread matches above, loose matches on Subject: below --
2014-02-21 0:59 Jingoo Han
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