From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from eu1sys200aog117.obsmtp.com ([207.126.144.143]:56690 "EHLO eu1sys200aog117.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750722AbaBTFX1 (ORCPT ); Thu, 20 Feb 2014 00:23:27 -0500 From: Mohit Kumar To: Cc: Mohit Kumar , Bjorn Helgaas , , Subject: [PATCH 1/2] PCI:designware:Fix comment for setting number of lanes Date: Thu, 20 Feb 2014 10:52:53 +0530 Message-ID: <1392873774-22249-1-git-send-email-mohit.kumar@st.com> Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org List-ID: Corrects comment for setting number of lanes. Signed-off-by: Mohit Kumar Cc: Jingoo Han Cc: Bjorn Helgaas Cc: spear-devel@list.st.com Cc: linux-pci@vger.kernel.org --- drivers/pci/host/pcie-designware.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 6d23d8c..391966f 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -766,7 +766,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) u32 membase; u32 memlimit; - /* set the number of lines as 4 */ + /* set the number of lanes */ dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); val &= ~PORT_LINK_MODE_MASK; switch (pp->lanes) { -- 1.7.0.1