From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-bn1blp0187.outbound.protection.outlook.com ([207.46.163.187]:48284 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756571AbaGIXFP (ORCPT ); Wed, 9 Jul 2014 19:05:15 -0400 From: To: , , CC: , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH 1/4 V3] irqchip: gic: Add binding probe for ARM GIC400 Date: Wed, 9 Jul 2014 18:05:01 -0500 Message-ID: <1404947104-21345-2-git-send-email-suravee.suthikulpanit@amd.com> In-Reply-To: <1404947104-21345-1-git-send-email-suravee.suthikulpanit@amd.com> References: <1404947104-21345-1-git-send-email-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-pci-owner@vger.kernel.org List-ID: From: Suravee Suthikulpanit Add new Irqchip declaration for GIC400. This was mentioned in gic binding documentation, but there is not code to support it. Signed-off-by: Suravee Suthikulpanit --- drivers/irqchip/irq-gic.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 508b815..ac8f7ea 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -1020,6 +1020,8 @@ gic_of_init(struct device_node *node, struct device_node *parent) gic_cnt++; return 0; } + +IRQCHIP_DECLARE(arm_gic_400, "arm,gic-400", gic_of_init); IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); -- 1.9.0