From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-by2on0139.outbound.protection.outlook.com ([207.46.100.139]:53504 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751183AbaIWEji (ORCPT ); Tue, 23 Sep 2014 00:39:38 -0400 From: Richard Zhu To: CC: , , , , , Richard Zhu Subject: [PATCH v2 2/5] PCI: imx6: wait the clocks to stabilize after ref_en Date: Tue, 23 Sep 2014 12:11:35 +0800 Message-ID: <1411445498-20250-3-git-send-email-r65037@freescale.com> In-Reply-To: <1411445498-20250-1-git-send-email-r65037@freescale.com> References: <1411445498-20250-1-git-send-email-r65037@freescale.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-pci-owner@vger.kernel.org List-ID: - a while delay is mandatory required after pcie_ref_clk_en is set. Otherwise, the system would be hang on imx6qdl ard boards, because that imx6qdl boards don't have the reset_gpio. - the clocks should be stable already after the "clk_prepare_enable" is return. So I think it's ok to move the usleep delay after the pcie_ref_en is set. Signed-off-by: Richard Zhu --- drivers/pci/host/pci-imx6.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 233fe8a..bc4222b 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -275,15 +275,15 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) goto err_pcie; } - /* allow the clocks to stabilize */ - usleep_range(200, 500); - /* power up core phy and enable ref clock */ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); + /* allow the clocks to stabilize */ + usleep_range(200, 500); + /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx6_pcie->reset_gpio)) { gpio_set_value(imx6_pcie->reset_gpio, 0); -- 1.9.1