From: Richard Zhu <r65037@freescale.com>
To: <linux-pci-owner@vger.kernel.org>
Cc: <linux-pci@vger.kernel.org>, <shawn.guo@freescale.com>,
<festevam@gmail.com>, <l.stach@pengutronix.de>,
<tharvey@gateworks.com>, Richard Zhu <r65037@freescale.com>
Subject: [PATCH v2 4/5] PCI: imx6: add imx6sx pcie related gpr bits definitions
Date: Tue, 23 Sep 2014 12:11:37 +0800 [thread overview]
Message-ID: <1411445498-20250-5-git-send-email-r65037@freescale.com> (raw)
In-Reply-To: <1411445498-20250-1-git-send-email-r65037@freescale.com>
Signed-off-by: Richard Zhu <r65037@freescale.com>
---
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index ff44374..f02875e 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -113,10 +113,12 @@
#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
#define IMX6Q_GPR1_PCIE_TEST_PD BIT(18)
+#define IMX6Q_GPR1_PCIE_TEST_PD_CLR 0x0
#define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17)
#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0
#define IMX6Q_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
#define IMX6Q_GPR1_PCIE_REF_CLK_EN BIT(16)
+#define IMX6Q_GPR1_PCIE_REF_CLK_CLR 0x0
#define IMX6Q_GPR1_USB_EXP_MODE BIT(15)
#define IMX6Q_GPR1_PCIE_INT BIT(14)
#define IMX6Q_GPR1_USB_OTG_ID_SEL_MASK BIT(13)
@@ -300,7 +302,9 @@
#define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24)
#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12)
#define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
+#define IMX6Q_GPR12_PCIE_CTL_2_CLR 0x0
#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4)
+#define IMX6Q_GPR12_LOS_LEVEL_9 (0x9 << 4)
#define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
@@ -395,4 +399,14 @@
#define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
#define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)
+/* For imx6sx iomux gpr register field define */
+#define IMX6SX_GPR5_PCIE_BTNRST BIT(19)
+#define IMX6SX_GPR5_PCIE_BTNRST_CLR 0x0
+#define IMX6SX_GPR5_PCIE_PERST BIT(18)
+#define IMX6SX_GPR5_PCIE_PERST_CLR 0x0
+
+#define IMX6SX_GPR12_PCIE_TEST_PD BIT(30)
+#define IMX6SX_GPR12_PCIE_TEST_PD_CLR 0x0
+#define IMX6SX_GPR12_RX_EQ_MASK (0x7 << 0)
+#define IMX6SX_GPR12_RX_EQ_2 (0x2 << 0)
#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
--
1.9.1
next prev parent reply other threads:[~2014-09-23 4:39 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-23 4:11 [PATCH v2]PCI: imx6: enable pcie on imx6sx sdb and imx6qdl sabreauto Richard Zhu
2014-09-23 4:11 ` [PATCH v2 1/5] PCI: imx6: enable pcie on " Richard Zhu
2014-09-23 9:19 ` Lucas Stach
2014-09-23 12:40 ` Fabio Estevam
2014-09-24 2:54 ` Hong-Xing.Zhu
2014-09-24 21:04 ` Fabio Estevam
2014-09-25 1:21 ` Hong-Xing.Zhu
2014-09-25 1:39 ` Fabio Estevam
2014-09-25 2:02 ` Hong-Xing.Zhu
2014-09-23 4:11 ` [PATCH v2 2/5] PCI: imx6: wait the clocks to stabilize after ref_en Richard Zhu
2014-09-23 9:56 ` Lucas Stach
2014-09-23 12:28 ` Tim Harvey
2014-09-25 5:21 ` Hong-Xing.Zhu
2014-10-01 18:00 ` Tim Harvey
2014-10-02 2:26 ` Hong-Xing.Zhu
2014-09-23 12:45 ` Fabio Estevam
2014-10-24 1:51 ` Fabio Estevam
2014-10-24 2:46 ` Richard.Zhu
2014-09-23 4:11 ` [PATCH v2 3/5] PCI: imx6: update dts and binding for imx6sx pcie Richard Zhu
2014-09-23 10:19 ` Lucas Stach
2014-09-24 9:43 ` Hong-Xing.Zhu
2014-09-23 4:11 ` Richard Zhu [this message]
2014-09-23 10:21 ` [PATCH v2 4/5] PCI: imx6: add imx6sx pcie related gpr bits definitions Lucas Stach
2014-09-24 4:45 ` Hong-Xing.Zhu
2014-09-23 4:11 ` [PATCH v2 5/5] PCI: imx6: add imx6sx pcie support Richard Zhu
2014-09-23 11:00 ` Lucas Stach
2014-09-24 7:09 ` Hong-Xing.Zhu
2014-09-24 9:46 ` Lucas Stach
2014-09-24 10:15 ` Hong-Xing.Zhu
2014-09-23 9:18 ` [PATCH v2]PCI: imx6: enable pcie on imx6sx sdb and imx6qdl sabreauto Lucas Stach
2014-09-23 9:29 ` Hong-Xing.Zhu
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