From: Richard Zhu <r65037@freescale.com>
To: <linux-pci-owner@vger.kernel.org>
Cc: <linux-pci@vger.kernel.org>, <shawn.guo@freescale.com>,
<festevam@gmail.com>, <l.stach@pengutronix.de>,
<tharvey@gateworks.com>, Richard Zhu <r65037@freescale.com>
Subject: [PATCH v3 5/9] PCI: imx6: add imx6sx pcie related gpr bits definitions
Date: Mon, 29 Sep 2014 13:03:13 +0800 [thread overview]
Message-ID: <1411966997-27118-6-git-send-email-r65037@freescale.com> (raw)
In-Reply-To: <1411966997-27118-1-git-send-email-r65037@freescale.com>
Signed-off-by: Richard Zhu <r65037@freescale.com>
---
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index ff44374..3273b87 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -301,6 +301,7 @@
#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12)
#define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4)
+#define IMX6Q_GPR12_LOS_LEVEL_9 (0x9 << 4)
#define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
@@ -395,4 +396,12 @@
#define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
#define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)
+/* For imx6sx iomux gpr register field define */
+#define IMX6SX_GPR5_PCIE_BTNRST BIT(19)
+#define IMX6SX_GPR5_PCIE_PERST BIT(18)
+
+#define IMX6SX_GPR12_PCIE_PM_TURN_OFF BIT(16)
+#define IMX6SX_GPR12_PCIE_TEST_PD BIT(30)
+#define IMX6SX_GPR12_RX_EQ_MASK (0x7 << 0)
+#define IMX6SX_GPR12_RX_EQ_2 (0x2 << 0)
#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
--
1.9.1
next prev parent reply other threads:[~2014-09-29 5:33 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-29 5:03 [PATCH v3]PCI: imx6: enable pcie on imx6sx sdb and imx6qdl sabreauto Richard Zhu
2014-09-29 5:03 ` [PATCH v3 1/9] PCI: imx6: wait the clocks to stabilize after ref_en Richard Zhu
2014-09-29 5:03 ` [PATCH v3 2/9] PCI: imx6: enable pcie on imx6qdl sabreauto Richard Zhu
2014-09-29 9:56 ` Lucas Stach
2014-09-30 2:18 ` Hong-Xing.Zhu
2014-09-29 5:03 ` [PATCH v3 3/9] PCI: imx6: update dts and binding for imx6sx pcie Richard Zhu
2014-09-29 10:13 ` Lucas Stach
2014-09-30 2:58 ` Hong-Xing.Zhu
2014-09-29 5:03 ` [PATCH v3 4/9] PCI: imx6: add syscon into gpc dts Richard Zhu
2014-09-29 5:03 ` Richard Zhu [this message]
2014-09-29 5:03 ` [PATCH v3 6/9] PCI: imx6: enable pcie on imx6sx sdb board Richard Zhu
2014-09-29 5:03 ` [PATCH v3 7/9] PCI: imx6: add imx6sx pcie support Richard Zhu
2014-09-29 10:18 ` Lucas Stach
2014-09-30 2:37 ` Hong-Xing.Zhu
2014-09-29 5:03 ` [PATCH v3 8/9] PCI: designware: refine setup_rc and add msi data restore Richard Zhu
2014-09-29 10:26 ` Lucas Stach
2014-09-29 5:03 ` [PATCH v3 9/9] PCI: imx6: Fix possible dead lock Richard Zhu
2014-09-29 10:38 ` Lucas Stach
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1411966997-27118-6-git-send-email-r65037@freescale.com \
--to=r65037@freescale.com \
--cc=festevam@gmail.com \
--cc=l.stach@pengutronix.de \
--cc=linux-pci-owner@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=shawn.guo@freescale.com \
--cc=tharvey@gateworks.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).