From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-bn1bbn0102.outbound.protection.outlook.com ([157.56.111.102]:47232 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752082AbaI3KHM (ORCPT ); Tue, 30 Sep 2014 06:07:12 -0400 From: Richard Zhu To: CC: , , , , , Richard Zhu Subject: [PATCH v4 10/10] ARM: imx6sx: enable pcie on imx6sx sdb board Date: Tue, 30 Sep 2014 17:36:44 +0800 Message-ID: <1412069804-17162-11-git-send-email-r65037@freescale.com> In-Reply-To: <1412069804-17162-1-git-send-email-r65037@freescale.com> References: <1412069804-17162-1-git-send-email-r65037@freescale.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-pci-owner@vger.kernel.org List-ID: Signed-off-by: Richard Zhu --- arch/arm/boot/dts/imx6sx-sdb.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index a3980d9..2976913 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -251,6 +251,13 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio2 0 0>; + status = "okay"; +}; + &ssi2 { status = "okay"; }; @@ -365,6 +372,12 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x17059 + >; + }; + pinctrl_vcc_sd3: vccsd3grp { fsl,pins = < MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 -- 1.9.1