[PATCH v5]PCI: imx6: enable pcie on imx6sx sdb and imx6qdl sabreauto.

[PATCH v5]PCI: imx6: enable pcie on imx6sx sdb and imx6qdl sabreauto.

[Richard Zhu]

Main changes since the v4:
1. add gpio controlled regulator for pcie on imx6sx sdb board.
2. in order to not break compilation, move designware modifications, before
imx6 pcie changes.
3. remove "PCI: imx6: Fix possible dead lock" from this series.
4. rename the pcie phy regulator from "pcie_regulator" to "pcie_phy_regulator".

[PATCH v5 1/9] PCI: designware: refine setup_rc and add msi data
[PATCH v5 2/9] PCI: designware: fix one potential assignment error of
[PATCH v5 3/9] PCI: imx6: wait the clocks to stabilize after ref_en
[PATCH v5 4/9] PCI: imx6: add imx6sx pcie support
[PATCH v5 5/9] ARM: imx6qdl: enable pcie on imx6qdl sabreauto
[PATCH v5 6/9] ARM: imx6: update dts and binding for imx6sx pcie
[PATCH v5 7/9] ARM: imx6sx: add syscon into gpc dts
[PATCH v5 8/9] ARM: imx6sx: add imx6sx pcie related gpr bits
[PATCH v5 9/9] ARM: imx6sx: enable pcie on imx6sx sdb board

[PATCH v5 1/9] PCI: designware: refine setup_rc and add msi data restore

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

- move "program correct class for RC" from dw_pcie_host_init()
to dw_pcie_setup_rc(). since this is RC setup, it's
better to contained in dw_pcie_setup_rc function.
Then, RC can be re-setup really by dw_pcie_setup_rc().
- add one re-store msi data function. Because that
pcie controller maybe powered off during system suspend,
and the msi data configuration would be lost.
this functions can be used to restore the msi data
during the resume callback.

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 drivers/pci/host/pcie-designware.c | 15 ++++++++++++---
 drivers/pci/host/pcie-designware.h |  1 +
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 538bbf3..ae1e6c5 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -194,6 +194,13 @@ void dw_pcie_msi_init(struct pcie_port *pp)
 	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
 }
 
+void dw_pcie_msi_cfg_restore(struct pcie_port *pp)
+{
+	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
+			virt_to_phys((void *)pp->msi_data));
+	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
+}
+
 static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
 {
 	int flag = 1;
@@ -570,9 +577,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 
 	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
 
-	/* program correct class for RC */
-	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
-
 	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
 	val |= PORT_LOGIC_SPEED_CHANGE;
 	dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
@@ -917,6 +921,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 	val = memlimit | membase;
 	dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
 
+	/* program correct class for RC */
+	dw_pcie_readl_rc(pp, PCI_CLASS_REVISION, &val);
+	val |= PCI_CLASS_BRIDGE_PCI << 16;
+	dw_pcie_writel_rc(pp, val, PCI_CLASS_REVISION);
+
 	/* setup command register */
 	dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
 	val &= 0xffff0000;
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index a476e60..bb75715 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -83,6 +83,7 @@ int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
 int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
 void dw_pcie_msi_init(struct pcie_port *pp);
+void dw_pcie_msi_cfg_restore(struct pcie_port *pp);
 int dw_pcie_link_up(struct pcie_port *pp);
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
-- 
1.9.1

Re: [PATCH v5 1/9] PCI: designware: refine setup_rc and add msi data restore

[Murali Karicheri]

On 10/10/2014 01:41 AM, Richard Zhu wrote:
> From: Richard Zhu<r65037@freescale.com>
>
> - move "program correct class for RC" from dw_pcie_host_init()
> to dw_pcie_setup_rc(). since this is RC setup, it's
> better to contained in dw_pcie_setup_rc function.
> Then, RC can be re-setup really by dw_pcie_setup_rc().
> - add one re-store msi data function. Because that
> pcie controller maybe powered off during system suspend,
> and the msi data configuration would be lost.
> this functions can be used to restore the msi data
> during the resume callback.
>
> Signed-off-by: Richard Zhu<richard.zhu@freescale.com>
> ---
>   drivers/pci/host/pcie-designware.c | 15 ++++++++++++---
>   drivers/pci/host/pcie-designware.h |  1 +
>   2 files changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 538bbf3..ae1e6c5 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -194,6 +194,13 @@ void dw_pcie_msi_init(struct pcie_port *pp)
>   	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
>   }
>
> +void dw_pcie_msi_cfg_restore(struct pcie_port *pp)
> +{
> +	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
> +			virt_to_phys((void *)pp->msi_data));
> +	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
> +}
Richard,

dw_msi_setup_irq() has the following code for setting msi_addr

	if (pp->ops->get_msi_addr)
		msg.address_lo = pp->ops->get_msi_addr(pp);
	else
		msg.address_lo = virt_to_phys((void *)pp->msi_data);

You need to do similar thing in dw_pcie_msi_cfg_restore() so that
it works across old (Keystone) and newer designware h/w

Murali
> +
>   static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
>   {
>   	int flag = 1;
> @@ -570,9 +577,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>
>   	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
>
> -	/* program correct class for RC */
> -	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
> -
>   	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4,&val);
>   	val |= PORT_LOGIC_SPEED_CHANGE;
>   	dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
> @@ -917,6 +921,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>   	val = memlimit | membase;
>   	dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
>
> +	/* program correct class for RC */
> +	dw_pcie_readl_rc(pp, PCI_CLASS_REVISION,&val);
> +	val |= PCI_CLASS_BRIDGE_PCI<<  16;
> +	dw_pcie_writel_rc(pp, val, PCI_CLASS_REVISION);
> +
>   	/* setup command register */
>   	dw_pcie_readl_rc(pp, PCI_COMMAND,&val);
>   	val&= 0xffff0000;
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index a476e60..bb75715 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -83,6 +83,7 @@ int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
>   int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
>   irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
>   void dw_pcie_msi_init(struct pcie_port *pp);
> +void dw_pcie_msi_cfg_restore(struct pcie_port *pp);
>   int dw_pcie_link_up(struct pcie_port *pp);
>   void dw_pcie_setup_rc(struct pcie_port *pp);
>   int dw_pcie_host_init(struct pcie_port *pp);


-- 
Murali Karicheri
Linux Kernel, Texas Instruments

RE: [PATCH v5 1/9] PCI: designware: refine setup_rc and add msi data restore

[Hong-Xing.Zhu]

Hi Murali:
Thanks for your comments.  And, sorry to miss your review comemnt before.


> -----Original Message-----
> From: Murali Karicheri [mailto:m-karicheri2@ti.com]
> Sent: Friday, October 10, 2014 10:42 PM
> To: Richard Zhu
> Cc: linux-pci@vger.kernel.org; Guo Shawn-R65073; festevam@gmail.com;
> l.stach@pengutronix.de; tharvey@gateworks.com; Zhu Richard-R65037
> Subject: Re: [PATCH v5 1/9] PCI: designware: refine setup_rc and add msi data
> restore
> 
> On 10/10/2014 01:41 AM, Richard Zhu wrote:
> > From: Richard Zhu<r65037@freescale.com>
> >
> > - move "program correct class for RC" from dw_pcie_host_init() to
> > dw_pcie_setup_rc(). since this is RC setup, it's better to contained
> > in dw_pcie_setup_rc function.
> > Then, RC can be re-setup really by dw_pcie_setup_rc().
> > - add one re-store msi data function. Because that pcie controller
> > maybe powered off during system suspend, and the msi data
> > configuration would be lost.
> > this functions can be used to restore the msi data during the resume
> > callback.
> >
> > Signed-off-by: Richard Zhu<richard.zhu@freescale.com>
> > ---
> >   drivers/pci/host/pcie-designware.c | 15 ++++++++++++---
> >   drivers/pci/host/pcie-designware.h |  1 +
> >   2 files changed, 13 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/pci/host/pcie-designware.c
> > b/drivers/pci/host/pcie-designware.c
> > index 538bbf3..ae1e6c5 100644
> > --- a/drivers/pci/host/pcie-designware.c
> > +++ b/drivers/pci/host/pcie-designware.c
> > @@ -194,6 +194,13 @@ void dw_pcie_msi_init(struct pcie_port *pp)
> >   	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
> >   }
> >
> > +void dw_pcie_msi_cfg_restore(struct pcie_port *pp) {
> > +	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
> > +			virt_to_phys((void *)pp->msi_data));
> > +	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); }
> Richard,
> 
> dw_msi_setup_irq() has the following code for setting msi_addr
> 
> 	if (pp->ops->get_msi_addr)
> 		msg.address_lo = pp->ops->get_msi_addr(pp);
> 	else
> 		msg.address_lo = virt_to_phys((void *)pp->msi_data);
> 
> You need to do similar thing in dw_pcie_msi_cfg_restore() so that it works
> across old (Keystone) and newer designware h/w
> 
> Murali
[Richard] Thanks a lot. Accepted.

> > +
> >   static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int
> *pos0)
> >   {
> >   	int flag = 1;
> > @@ -570,9 +577,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
> >
> >   	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
> >
> > -	/* program correct class for RC */
> > -	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
> > -
> >   	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4,&val);
> >   	val |= PORT_LOGIC_SPEED_CHANGE;
> >   	dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); @@
> > -917,6 +921,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> >   	val = memlimit | membase;
> >   	dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
> >
> > +	/* program correct class for RC */
> > +	dw_pcie_readl_rc(pp, PCI_CLASS_REVISION,&val);
> > +	val |= PCI_CLASS_BRIDGE_PCI<<  16;
> > +	dw_pcie_writel_rc(pp, val, PCI_CLASS_REVISION);
> > +
> >   	/* setup command register */
> >   	dw_pcie_readl_rc(pp, PCI_COMMAND,&val);
> >   	val&= 0xffff0000;
> > diff --git a/drivers/pci/host/pcie-designware.h
> > b/drivers/pci/host/pcie-designware.h
> > index a476e60..bb75715 100644
> > --- a/drivers/pci/host/pcie-designware.h
> > +++ b/drivers/pci/host/pcie-designware.h
> > @@ -83,6 +83,7 @@ int dw_pcie_cfg_read(void __iomem *addr, int where, int
> size, u32 *val);
> >   int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
> >   irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
> >   void dw_pcie_msi_init(struct pcie_port *pp);
> > +void dw_pcie_msi_cfg_restore(struct pcie_port *pp);
> >   int dw_pcie_link_up(struct pcie_port *pp);
> >   void dw_pcie_setup_rc(struct pcie_port *pp);
> >   int dw_pcie_host_init(struct pcie_port *pp);
> 
> 
> --
> Murali Karicheri
> Linux Kernel, Texas Instruments

Re: [PATCH v5 1/9] PCI: designware: refine setup_rc and add msi data restore

[Murali Karicheri]

On 10/19/2014 10:59 PM, Hong-Xing.Zhu@freescale.com wrote:
> Hi Murali:
> Thanks for your comments.  And, sorry to miss your review comemnt before.

No issues.

Regards,

Murali
>
>
>> -----Original Message-----
>> From: Murali Karicheri [mailto:m-karicheri2@ti.com]
>> Sent: Friday, October 10, 2014 10:42 PM
>> To: Richard Zhu
>> Cc: linux-pci@vger.kernel.org; Guo Shawn-R65073; festevam@gmail.com;
>> l.stach@pengutronix.de; tharvey@gateworks.com; Zhu Richard-R65037
>> Subject: Re: [PATCH v5 1/9] PCI: designware: refine setup_rc and add msi data
>> restore
>>
>> On 10/10/2014 01:41 AM, Richard Zhu wrote:
>>> From: Richard Zhu<r65037@freescale.com>
>>>
>>> - move "program correct class for RC" from dw_pcie_host_init() to
>>> dw_pcie_setup_rc(). since this is RC setup, it's better to contained
>>> in dw_pcie_setup_rc function.
>>> Then, RC can be re-setup really by dw_pcie_setup_rc().
>>> - add one re-store msi data function. Because that pcie controller
>>> maybe powered off during system suspend, and the msi data
>>> configuration would be lost.
>>> this functions can be used to restore the msi data during the resume
>>> callback.
>>>
>>> Signed-off-by: Richard Zhu<richard.zhu@freescale.com>
>>> ---
>>>    drivers/pci/host/pcie-designware.c | 15 ++++++++++++---
>>>    drivers/pci/host/pcie-designware.h |  1 +
>>>    2 files changed, 13 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/pci/host/pcie-designware.c
>>> b/drivers/pci/host/pcie-designware.c
>>> index 538bbf3..ae1e6c5 100644
>>> --- a/drivers/pci/host/pcie-designware.c
>>> +++ b/drivers/pci/host/pcie-designware.c
>>> @@ -194,6 +194,13 @@ void dw_pcie_msi_init(struct pcie_port *pp)
>>>    	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
>>>    }
>>>
>>> +void dw_pcie_msi_cfg_restore(struct pcie_port *pp) {
>>> +	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
>>> +			virt_to_phys((void *)pp->msi_data));
>>> +	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); }
>> Richard,
>>
>> dw_msi_setup_irq() has the following code for setting msi_addr
>>
>> 	if (pp->ops->get_msi_addr)
>> 		msg.address_lo = pp->ops->get_msi_addr(pp);
>> 	else
>> 		msg.address_lo = virt_to_phys((void *)pp->msi_data);
>>
>> You need to do similar thing in dw_pcie_msi_cfg_restore() so that it works
>> across old (Keystone) and newer designware h/w
>>
>> Murali
> [Richard] Thanks a lot. Accepted.
>
>>> +
>>>    static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int
>> *pos0)
>>>    {
>>>    	int flag = 1;
>>> @@ -570,9 +577,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>>>
>>>    	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
>>>
>>> -	/* program correct class for RC */
>>> -	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
>>> -
>>>    	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4,&val);
>>>    	val |= PORT_LOGIC_SPEED_CHANGE;
>>>    	dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); @@
>>> -917,6 +921,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>>>    	val = memlimit | membase;
>>>    	dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
>>>
>>> +	/* program correct class for RC */
>>> +	dw_pcie_readl_rc(pp, PCI_CLASS_REVISION,&val);
>>> +	val |= PCI_CLASS_BRIDGE_PCI<<   16;
>>> +	dw_pcie_writel_rc(pp, val, PCI_CLASS_REVISION);
>>> +
>>>    	/* setup command register */
>>>    	dw_pcie_readl_rc(pp, PCI_COMMAND,&val);
>>>    	val&= 0xffff0000;
>>> diff --git a/drivers/pci/host/pcie-designware.h
>>> b/drivers/pci/host/pcie-designware.h
>>> index a476e60..bb75715 100644
>>> --- a/drivers/pci/host/pcie-designware.h
>>> +++ b/drivers/pci/host/pcie-designware.h
>>> @@ -83,6 +83,7 @@ int dw_pcie_cfg_read(void __iomem *addr, int where, int
>> size, u32 *val);
>>>    int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
>>>    irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
>>>    void dw_pcie_msi_init(struct pcie_port *pp);
>>> +void dw_pcie_msi_cfg_restore(struct pcie_port *pp);
>>>    int dw_pcie_link_up(struct pcie_port *pp);
>>>    void dw_pcie_setup_rc(struct pcie_port *pp);
>>>    int dw_pcie_host_init(struct pcie_port *pp);
>>
>>
>> --
>> Murali Karicheri
>> Linux Kernel, Texas Instruments


-- 
Murali Karicheri
Linux Kernel, Texas Instruments

Re: [PATCH v5 1/9] PCI: designware: refine setup_rc and add msi data restore

[Lucas Stach]

Hi Richard,

Am Freitag, den 10.10.2014, 13:41 +0800 schrieb Richard Zhu:
> From: Richard Zhu <r65037@freescale.com>
> 
> - move "program correct class for RC" from dw_pcie_host_init()
> to dw_pcie_setup_rc(). since this is RC setup, it's
> better to contained in dw_pcie_setup_rc function.
> Then, RC can be re-setup really by dw_pcie_setup_rc().
> - add one re-store msi data function. Because that
> pcie controller maybe powered off during system suspend,
> and the msi data configuration would be lost.
> this functions can be used to restore the msi data
> during the resume callback.
> 
> Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
> ---
>  drivers/pci/host/pcie-designware.c | 15 ++++++++++++---
>  drivers/pci/host/pcie-designware.h |  1 +
>  2 files changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 538bbf3..ae1e6c5 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -194,6 +194,13 @@ void dw_pcie_msi_init(struct pcie_port *pp)
>  	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
>  }
>  
> +void dw_pcie_msi_cfg_restore(struct pcie_port *pp)
> +{
> +	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
> +			virt_to_phys((void *)pp->msi_data));
> +	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
> +}
> +
>  static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
>  {
>  	int flag = 1;
> @@ -570,9 +577,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>  
>  	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
>  
> -	/* program correct class for RC */
> -	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
> -
>  	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
>  	val |= PORT_LOGIC_SPEED_CHANGE;
>  	dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
> @@ -917,6 +921,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>  	val = memlimit | membase;
>  	dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
>  
> +	/* program correct class for RC */
> +	dw_pcie_readl_rc(pp, PCI_CLASS_REVISION, &val);
> +	val |= PCI_CLASS_BRIDGE_PCI << 16;
> +	dw_pcie_writel_rc(pp, val, PCI_CLASS_REVISION);
> +
I've already said on the last revision of this patch that you should not
change the way this setup is done, but just move it. Please make sure to
be more careful when resending your patches. Silently dropping the
review feedback is wasting everyones time.

So this patch is still clearly a NACK.

>  	/* setup command register */
>  	dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
>  	val &= 0xffff0000;
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index a476e60..bb75715 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -83,6 +83,7 @@ int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
>  int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
>  irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
>  void dw_pcie_msi_init(struct pcie_port *pp);
> +void dw_pcie_msi_cfg_restore(struct pcie_port *pp);
>  int dw_pcie_link_up(struct pcie_port *pp);
>  void dw_pcie_setup_rc(struct pcie_port *pp);
>  int dw_pcie_host_init(struct pcie_port *pp);

[PATCH v5 2/9] PCI: designware: fix one potential assignment error of cfg start

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

if va_cfg0_base/va_cfg1_base are initialized by
designware core, the pp->cfg.start is not initialized
properly, when IORESOURCE_MEM "config" is represented
as cfg space resource.
solution: assign cfg_res->start to pp->cfg.start.

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 drivers/pci/host/pcie-designware.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index ae1e6c5..f1f127f 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -444,6 +444,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 	if (cfg_res) {
 		pp->config.cfg0_size = resource_size(cfg_res)/2;
 		pp->config.cfg1_size = resource_size(cfg_res)/2;
+		pp->cfg.start = cfg_res->start;
 		pp->cfg0_base = cfg_res->start;
 		pp->cfg1_base = cfg_res->start + pp->config.cfg0_size;
 
-- 
1.9.1

[PATCH v5 3/9] PCI: imx6: wait the clocks to stabilize after ref_en

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

For boards without a reset gpio we skip the delay between enabling
the pcie_ref_clk and touching the RC registers for configuration.
System would be hangs when the clocks are not yet settled in the DW
PCIe core. So we need to make sure that there is always an
appropriate delay between those two actions.

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
---
 drivers/pci/host/pci-imx6.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index 233fe8a..eac96fb 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -275,15 +275,22 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 		goto err_pcie;
 	}
 
-	/* allow the clocks to stabilize */
-	usleep_range(200, 500);
-
 	/* power up core phy and enable ref clock */
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
+	/*
+	 * the async reset input need ref clock to sync internally,
+	 * when the ref clock comes after reset, internal synced
+	 * reset time is too short , cannot meet the requirement.
+	 * add one ~10us delay here.
+	 */
+	udelay(10);
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
 
+	/* allow the clocks to stabilize */
+	usleep_range(200, 500);
+
 	/* Some boards don't have PCIe reset GPIO. */
 	if (gpio_is_valid(imx6_pcie->reset_gpio)) {
 		gpio_set_value(imx6_pcie->reset_gpio, 0);
-- 
1.9.1

[PATCH v5 4/9] PCI: imx6: add imx6sx pcie support

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

- imx6sx pcie has its own standalone pcie power supply.
In order to turn on the imx6sx pcie power during
initialization. Add the pcie regulator and the gpc regmap
into the imx6sx pcie structure.
- imx6sx pcie has the new added reset mechanism, add the
reset operations into the initialization.
- Register one PM call-back, enter/exit L2 state of the ASPM
during system suspend/resume.
- disp_axi clock is required by pcie inbound axi port actually.
Add one more clock named pcie_inbound_axi for imx6sx pcie.

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 drivers/pci/host/pci-imx6.c | 161 +++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 143 insertions(+), 18 deletions(-)

diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index eac96fb..5ece4e1 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -22,8 +22,10 @@
 #include <linux/pci.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
 #include <linux/resource.h>
 #include <linux/signal.h>
+#include <linux/syscore_ops.h>
 #include <linux/types.h>
 #include <linux/interrupt.h>
 
@@ -35,11 +37,15 @@ struct imx6_pcie {
 	int			reset_gpio;
 	struct clk		*pcie_bus;
 	struct clk		*pcie_phy;
+	struct clk		*pcie_inbound_axi;
 	struct clk		*pcie;
 	struct pcie_port	pp;
 	struct regmap		*iomuxc_gpr;
+	struct regmap		*gpc_ips_reg;
+	struct regulator	*pcie_phy_regulator;
 	void __iomem		*mem_base;
 };
+static struct imx6_pcie *imx6_pcie;
 
 /* PCIe Root Complex registers (memory-mapped) */
 #define PCIE_RC_LCR				0x7c
@@ -77,6 +83,18 @@ struct imx6_pcie {
 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
 
+/* GPC PCIE PHY bit definitions */
+#define GPC_CNTR			0
+#define GPC_CNTR_PCIE_PHY_PUP_REQ	BIT(7)
+
+static inline bool is_imx6sx_pcie(struct imx6_pcie *imx6_pcie)
+{
+	struct pcie_port *pp = &imx6_pcie->pp;
+	struct device_node *np = pp->dev->of_node;
+
+	return of_device_is_compatible(np, "fsl,imx6sx-pcie");
+}
+
 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
 {
 	u32 val;
@@ -275,18 +293,29 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 		goto err_pcie;
 	}
 
-	/* power up core phy and enable ref clock */
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
-	/*
-	 * the async reset input need ref clock to sync internally,
-	 * when the ref clock comes after reset, internal synced
-	 * reset time is too short , cannot meet the requirement.
-	 * add one ~10us delay here.
-	 */
-	udelay(10);
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
+	if (is_imx6sx_pcie(imx6_pcie)) {
+		ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
+		if (ret) {
+			dev_err(pp->dev, "unable to enable pcie clock\n");
+			goto err_inbound_axi;
+		}
+
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				IMX6SX_GPR12_PCIE_TEST_PD, 0);
+	} else {
+		/* power up core phy and enable ref clock */
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+				IMX6Q_GPR1_PCIE_TEST_PD, 0);
+		/*
+		 * the async reset input need ref clock to sync internally,
+		 * when the ref clock comes after reset, internal synced
+		 * reset time is too short , cannot meet the requirement.
+		 * add one ~10us delay here.
+		 */
+		udelay(10);
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+				IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
+	}
 
 	/* allow the clocks to stabilize */
 	usleep_range(200, 500);
@@ -297,8 +326,19 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 		msleep(100);
 		gpio_set_value(imx6_pcie->reset_gpio, 1);
 	}
+
+	/*
+	 * Release the PCIe PHY reset here, that we have set in
+	 * imx6_pcie_init_phy() now
+	 */
+	if (is_imx6sx_pcie(imx6_pcie))
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+				IMX6SX_GPR5_PCIE_BTNRST, 0);
+
 	return 0;
 
+err_inbound_axi:
+	clk_disable_unprepare(imx6_pcie->pcie);
 err_pcie:
 	clk_disable_unprepare(imx6_pcie->pcie_bus);
 err_pcie_bus:
@@ -311,6 +351,26 @@ err_pcie_phy:
 static void imx6_pcie_init_phy(struct pcie_port *pp)
 {
 	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
+	int ret;
+
+	/* Power up the separate domain available on i.MX6SX */
+	if (is_imx6sx_pcie(imx6_pcie)) {
+		/* Force PCIe PHY reset */
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+				IMX6SX_GPR5_PCIE_BTNRST,
+				IMX6SX_GPR5_PCIE_BTNRST);
+
+		regmap_update_bits(imx6_pcie->gpc_ips_reg, GPC_CNTR,
+				GPC_CNTR_PCIE_PHY_PUP_REQ,
+				GPC_CNTR_PCIE_PHY_PUP_REQ);
+		regulator_set_voltage(imx6_pcie->pcie_phy_regulator,
+				1100000, 1100000);
+		ret = regulator_enable(imx6_pcie->pcie_phy_regulator);
+		if (ret)
+			dev_info(pp->dev, "failed to enable pcie regulator.\n");
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				IMX6SX_GPR12_RX_EQ_MASK, IMX6SX_GPR12_RX_EQ_2);
+	}
 
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 			IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
@@ -319,7 +379,7 @@ static void imx6_pcie_init_phy(struct pcie_port *pp)
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 			IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
-			IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
+			IMX6Q_GPR12_LOS_LEVEL, IMX6Q_GPR12_LOS_LEVEL_9);
 
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 			IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
@@ -377,7 +437,8 @@ static int imx6_pcie_start_link(struct pcie_port *pp)
 
 	/* Start LTSSM. */
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
-			IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
+			IMX6Q_GPR12_PCIE_CTL_2,
+			IMX6Q_GPR12_PCIE_CTL_2);
 
 	ret = imx6_pcie_wait_for_link(pp);
 	if (ret)
@@ -553,9 +614,50 @@ static int __init imx6_add_pcie_port(struct pcie_port *pp,
 	return 0;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int pci_imx_suspend(void)
+{
+	if (is_imx6sx_pcie(imx6_pcie)) {
+		/* PM_TURN_OFF */
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				IMX6SX_GPR12_PCIE_PM_TURN_OFF,
+				IMX6SX_GPR12_PCIE_PM_TURN_OFF);
+		udelay(10);
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
+	}
+
+	return 0;
+}
+
+static void pci_imx_resume(void)
+{
+	struct pcie_port *pp = &imx6_pcie->pp;
+
+	if (is_imx6sx_pcie(imx6_pcie)) {
+		/* Reset iMX6SX PCIe */
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+				IMX6SX_GPR5_PCIE_PERST, IMX6SX_GPR5_PCIE_PERST);
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+				IMX6SX_GPR5_PCIE_PERST, 0);
+		/*
+		 * controller maybe turn off, re-configure again
+		 */
+		dw_pcie_setup_rc(pp);
+
+		if (IS_ENABLED(CONFIG_PCI_MSI))
+			dw_pcie_msi_cfg_restore(pp);
+	}
+}
+
+static struct syscore_ops pci_imx_syscore_ops = {
+	.suspend = pci_imx_suspend,
+	.resume = pci_imx_resume,
+};
+#endif
+
 static int __init imx6_pcie_probe(struct platform_device *pdev)
 {
-	struct imx6_pcie *imx6_pcie;
 	struct pcie_port *pp;
 	struct device_node *np = pdev->dev.of_node;
 	struct resource *dbi_base;
@@ -610,9 +712,28 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
 		return PTR_ERR(imx6_pcie->pcie);
 	}
 
-	/* Grab GPR config register range */
-	imx6_pcie->iomuxc_gpr =
-		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+	if (is_imx6sx_pcie(imx6_pcie)) {
+		imx6_pcie->pcie_inbound_axi = devm_clk_get(&pdev->dev,
+				"pcie_inbound_axi");
+		if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
+			dev_err(&pdev->dev,
+				"pcie clock source missing or invalid\n");
+			return PTR_ERR(imx6_pcie->pcie_inbound_axi);
+		}
+
+		imx6_pcie->pcie_phy_regulator = devm_regulator_get(pp->dev,
+				"pcie-phy");
+
+		imx6_pcie->iomuxc_gpr =
+			 syscon_regmap_lookup_by_compatible
+			 ("fsl,imx6sx-iomuxc-gpr");
+		imx6_pcie->gpc_ips_reg =
+			 syscon_regmap_lookup_by_compatible("fsl,imx6sx-gpc");
+	} else {
+		imx6_pcie->iomuxc_gpr =
+			syscon_regmap_lookup_by_compatible
+			("fsl,imx6q-iomuxc-gpr");
+	}
 	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
 		dev_err(&pdev->dev, "unable to find iomuxc registers\n");
 		return PTR_ERR(imx6_pcie->iomuxc_gpr);
@@ -623,6 +744,9 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
 		return ret;
 
 	platform_set_drvdata(pdev, imx6_pcie);
+#ifdef CONFIG_PM_SLEEP
+	register_syscore_ops(&pci_imx_syscore_ops);
+#endif
 	return 0;
 }
 
@@ -636,6 +760,7 @@ static void imx6_pcie_shutdown(struct platform_device *pdev)
 
 static const struct of_device_id imx6_pcie_of_match[] = {
 	{ .compatible = "fsl,imx6q-pcie", },
+	{ .compatible = "fsl,imx6sx-pcie", },
 	{},
 };
 MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
-- 
1.9.1

Re: [PATCH v5 4/9] PCI: imx6: add imx6sx pcie support

[Fabio Estevam]

On Fri, Oct 10, 2014 at 2:41 AM, Richard Zhu <richard.zhu@freescale.com> wrote:

>  static void imx6_pcie_init_phy(struct pcie_port *pp)
>  {
>         struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
> +       int ret;
> +
> +       /* Power up the separate domain available on i.MX6SX */
> +       if (is_imx6sx_pcie(imx6_pcie)) {
> +               /* Force PCIe PHY reset */
> +               regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
> +                               IMX6SX_GPR5_PCIE_BTNRST,
> +                               IMX6SX_GPR5_PCIE_BTNRST);
> +
> +               regmap_update_bits(imx6_pcie->gpc_ips_reg, GPC_CNTR,
> +                               GPC_CNTR_PCIE_PHY_PUP_REQ,
> +                               GPC_CNTR_PCIE_PHY_PUP_REQ);
> +               regulator_set_voltage(imx6_pcie->pcie_phy_regulator,
> +                               1100000, 1100000);
> +               ret = regulator_enable(imx6_pcie->pcie_phy_regulator);
> +               if (ret)
> +                       dev_info(pp->dev, "failed to enable pcie regulator.\n");

You should 'return ret' in the case of error.

RE: [PATCH v5 4/9] PCI: imx6: add imx6sx pcie support

[Hong-Xing.Zhu]

PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBGYWJpbyBFc3RldmFtIFttYWls
dG86ZmVzdGV2YW1AZ21haWwuY29tXQ0KPiBTZW50OiBGcmlkYXksIE9jdG9iZXIgMTAsIDIwMTQg
MTA6NTUgUE0NCj4gVG86IFJpY2hhcmQgWmh1DQo+IENjOiBsaW51eC1wY2lAdmdlci5rZXJuZWwu
b3JnOyBHdW8gU2hhd24tUjY1MDczOyBMdWNhcyBTdGFjaDsgVGltIEhhcnZleTsgWmh1DQo+IFJp
Y2hhcmQtUjY1MDM3DQo+IFN1YmplY3Q6IFJlOiBbUEFUQ0ggdjUgNC85XSBQQ0k6IGlteDY6IGFk
ZCBpbXg2c3ggcGNpZSBzdXBwb3J0DQo+IA0KPiBPbiBGcmksIE9jdCAxMCwgMjAxNCBhdCAyOjQx
IEFNLCBSaWNoYXJkIFpodSA8cmljaGFyZC56aHVAZnJlZXNjYWxlLmNvbT4gd3JvdGU6DQo+IA0K
PiA+ICBzdGF0aWMgdm9pZCBpbXg2X3BjaWVfaW5pdF9waHkoc3RydWN0IHBjaWVfcG9ydCAqcHAp
ICB7DQo+ID4gICAgICAgICBzdHJ1Y3QgaW14Nl9wY2llICppbXg2X3BjaWUgPSB0b19pbXg2X3Bj
aWUocHApOw0KPiA+ICsgICAgICAgaW50IHJldDsNCj4gPiArDQo+ID4gKyAgICAgICAvKiBQb3dl
ciB1cCB0aGUgc2VwYXJhdGUgZG9tYWluIGF2YWlsYWJsZSBvbiBpLk1YNlNYICovDQo+ID4gKyAg
ICAgICBpZiAoaXNfaW14NnN4X3BjaWUoaW14Nl9wY2llKSkgew0KPiA+ICsgICAgICAgICAgICAg
ICAvKiBGb3JjZSBQQ0llIFBIWSByZXNldCAqLw0KPiA+ICsgICAgICAgICAgICAgICByZWdtYXBf
dXBkYXRlX2JpdHMoaW14Nl9wY2llLT5pb211eGNfZ3ByLCBJT01VWENfR1BSNSwNCj4gPiArICAg
ICAgICAgICAgICAgICAgICAgICAgICAgICAgIElNWDZTWF9HUFI1X1BDSUVfQlROUlNULA0KPiA+
ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgSU1YNlNYX0dQUjVfUENJRV9CVE5SU1Qp
Ow0KPiA+ICsNCj4gPiArICAgICAgICAgICAgICAgcmVnbWFwX3VwZGF0ZV9iaXRzKGlteDZfcGNp
ZS0+Z3BjX2lwc19yZWcsIEdQQ19DTlRSLA0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAg
ICAgICAgR1BDX0NOVFJfUENJRV9QSFlfUFVQX1JFUSwNCj4gPiArICAgICAgICAgICAgICAgICAg
ICAgICAgICAgICAgIEdQQ19DTlRSX1BDSUVfUEhZX1BVUF9SRVEpOw0KPiA+ICsgICAgICAgICAg
ICAgICByZWd1bGF0b3Jfc2V0X3ZvbHRhZ2UoaW14Nl9wY2llLT5wY2llX3BoeV9yZWd1bGF0b3Is
DQo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAxMTAwMDAwLCAxMTAwMDAwKTsN
Cj4gPiArICAgICAgICAgICAgICAgcmV0ID0gcmVndWxhdG9yX2VuYWJsZShpbXg2X3BjaWUtPnBj
aWVfcGh5X3JlZ3VsYXRvcik7DQo+ID4gKyAgICAgICAgICAgICAgIGlmIChyZXQpDQo+ID4gKyAg
ICAgICAgICAgICAgICAgICAgICAgZGV2X2luZm8ocHAtPmRldiwgImZhaWxlZCB0byBlbmFibGUg
cGNpZQ0KPiA+ICsgcmVndWxhdG9yLlxuIik7DQo+IA0KPiBZb3Ugc2hvdWxkICdyZXR1cm4gcmV0
JyBpbiB0aGUgY2FzZSBvZiBlcnJvci4NCltSaWNoYXJkXSBPay4NCg0KQmVzdCBSZWdhcmRzDQpS
aWNoYXJkIFpodQ0KDQo=

Re: [PATCH v5 4/9] PCI: imx6: add imx6sx pcie support

[Lucas Stach]

Am Freitag, den 10.10.2014, 13:41 +0800 schrieb Richard Zhu:
> From: Richard Zhu <r65037@freescale.com>
> 
> - imx6sx pcie has its own standalone pcie power supply.
> In order to turn on the imx6sx pcie power during
> initialization. Add the pcie regulator and the gpc regmap
> into the imx6sx pcie structure.
> - imx6sx pcie has the new added reset mechanism, add the
> reset operations into the initialization.
> - Register one PM call-back, enter/exit L2 state of the ASPM
> during system suspend/resume.
> - disp_axi clock is required by pcie inbound axi port actually.
> Add one more clock named pcie_inbound_axi for imx6sx pcie.

> Signed-off-by: Richard Zhu <richard.zhu@freescale.com>

In addition to Fabios comment I have one additional nitpick below and
also you didn't include all the feedback from the last round.

> ---
>  drivers/pci/host/pci-imx6.c | 161 +++++++++++++++++++++++++++++++++++++++-----
>  1 file changed, 143 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
> index eac96fb..5ece4e1 100644
> --- a/drivers/pci/host/pci-imx6.c
> +++ b/drivers/pci/host/pci-imx6.c
> @@ -22,8 +22,10 @@
>  #include <linux/pci.h>
>  #include <linux/platform_device.h>
>  #include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
>  #include <linux/resource.h>
>  #include <linux/signal.h>
> +#include <linux/syscore_ops.h>
>  #include <linux/types.h>
>  #include <linux/interrupt.h>
>  
> @@ -35,11 +37,15 @@ struct imx6_pcie {
>  	int			reset_gpio;
>  	struct clk		*pcie_bus;
>  	struct clk		*pcie_phy;
> +	struct clk		*pcie_inbound_axi;
>  	struct clk		*pcie;
>  	struct pcie_port	pp;
>  	struct regmap		*iomuxc_gpr;
> +	struct regmap		*gpc_ips_reg;
> +	struct regulator	*pcie_phy_regulator;
>  	void __iomem		*mem_base;
>  };
> +static struct imx6_pcie *imx6_pcie;

Remove this static struct. I've already said on the last version that
this is completely backwards.

>  
>  /* PCIe Root Complex registers (memory-mapped) */
>  #define PCIE_RC_LCR				0x7c
> @@ -77,6 +83,18 @@ struct imx6_pcie {
>  #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
>  #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
>  
> +/* GPC PCIE PHY bit definitions */
> +#define GPC_CNTR			0
> +#define GPC_CNTR_PCIE_PHY_PUP_REQ	BIT(7)
> +
> +static inline bool is_imx6sx_pcie(struct imx6_pcie *imx6_pcie)
> +{
> +	struct pcie_port *pp = &imx6_pcie->pp;
> +	struct device_node *np = pp->dev->of_node;
> +
> +	return of_device_is_compatible(np, "fsl,imx6sx-pcie");
> +}
> +
>  static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
>  {
>  	u32 val;
> @@ -275,18 +293,29 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
>  		goto err_pcie;
>  	}
>  
> -	/* power up core phy and enable ref clock */
> -	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> -			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
> -	/*
> -	 * the async reset input need ref clock to sync internally,
> -	 * when the ref clock comes after reset, internal synced
> -	 * reset time is too short , cannot meet the requirement.
> -	 * add one ~10us delay here.
> -	 */
> -	udelay(10);
> -	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> -			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
> +	if (is_imx6sx_pcie(imx6_pcie)) {
> +		ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
> +		if (ret) {
> +			dev_err(pp->dev, "unable to enable pcie clock\n");
> +			goto err_inbound_axi;
> +		}
> +
> +		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> +				IMX6SX_GPR12_PCIE_TEST_PD, 0);
> +	} else {
> +		/* power up core phy and enable ref clock */
> +		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> +				IMX6Q_GPR1_PCIE_TEST_PD, 0);
> +		/*
> +		 * the async reset input need ref clock to sync internally,
> +		 * when the ref clock comes after reset, internal synced
> +		 * reset time is too short , cannot meet the requirement.
> +		 * add one ~10us delay here.
> +		 */
> +		udelay(10);
> +		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> +				IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);

[...]

Please use IMX6Q_GPR1_PCIE_REF_CLK_EN instead of 1 << 16 here. I know
this is only moved code, but as you are touching it anyway this cleanup
should be folded in.

RE: [PATCH v5 4/9] PCI: imx6: add imx6sx pcie support

[Hong-Xing.Zhu]

SGkgTHVjYXM6DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogbGludXgt
cGNpLW93bmVyQHZnZXIua2VybmVsLm9yZyBbbWFpbHRvOmxpbnV4LXBjaS1vd25lckB2Z2VyLmtl
cm5lbC5vcmddDQo+IE9uIEJlaGFsZiBPZiBMdWNhcyBTdGFjaA0KPiBTZW50OiBTdW5kYXksIE9j
dG9iZXIgMTIsIDIwMTQgMTA6MjggUE0NCj4gVG86IFJpY2hhcmQgWmh1DQo+IENjOiBsaW51eC1w
Y2lAdmdlci5rZXJuZWwub3JnOyBHdW8gU2hhd24tUjY1MDczOyBmZXN0ZXZhbUBnbWFpbC5jb207
DQo+IHRoYXJ2ZXlAZ2F0ZXdvcmtzLmNvbTsgWmh1IFJpY2hhcmQtUjY1MDM3DQo+IFN1YmplY3Q6
IFJlOiBbUEFUQ0ggdjUgNC85XSBQQ0k6IGlteDY6IGFkZCBpbXg2c3ggcGNpZSBzdXBwb3J0DQo+
IA0KPiBBbSBGcmVpdGFnLCBkZW4gMTAuMTAuMjAxNCwgMTM6NDEgKzA4MDAgc2NocmllYiBSaWNo
YXJkIFpodToNCj4gPiBGcm9tOiBSaWNoYXJkIFpodSA8cjY1MDM3QGZyZWVzY2FsZS5jb20+DQo+
ID4NCj4gPiAtIGlteDZzeCBwY2llIGhhcyBpdHMgb3duIHN0YW5kYWxvbmUgcGNpZSBwb3dlciBz
dXBwbHkuDQo+ID4gSW4gb3JkZXIgdG8gdHVybiBvbiB0aGUgaW14NnN4IHBjaWUgcG93ZXIgZHVy
aW5nIGluaXRpYWxpemF0aW9uLiBBZGQNCj4gPiB0aGUgcGNpZSByZWd1bGF0b3IgYW5kIHRoZSBn
cGMgcmVnbWFwIGludG8gdGhlIGlteDZzeCBwY2llIHN0cnVjdHVyZS4NCj4gPiAtIGlteDZzeCBw
Y2llIGhhcyB0aGUgbmV3IGFkZGVkIHJlc2V0IG1lY2hhbmlzbSwgYWRkIHRoZSByZXNldA0KPiA+
IG9wZXJhdGlvbnMgaW50byB0aGUgaW5pdGlhbGl6YXRpb24uDQo+ID4gLSBSZWdpc3RlciBvbmUg
UE0gY2FsbC1iYWNrLCBlbnRlci9leGl0IEwyIHN0YXRlIG9mIHRoZSBBU1BNIGR1cmluZw0KPiA+
IHN5c3RlbSBzdXNwZW5kL3Jlc3VtZS4NCj4gPiAtIGRpc3BfYXhpIGNsb2NrIGlzIHJlcXVpcmVk
IGJ5IHBjaWUgaW5ib3VuZCBheGkgcG9ydCBhY3R1YWxseS4NCj4gPiBBZGQgb25lIG1vcmUgY2xv
Y2sgbmFtZWQgcGNpZV9pbmJvdW5kX2F4aSBmb3IgaW14NnN4IHBjaWUuDQo+IA0KPiA+IFNpZ25l
ZC1vZmYtYnk6IFJpY2hhcmQgWmh1IDxyaWNoYXJkLnpodUBmcmVlc2NhbGUuY29tPg0KPiANCj4g
SW4gYWRkaXRpb24gdG8gRmFiaW9zIGNvbW1lbnQgSSBoYXZlIG9uZSBhZGRpdGlvbmFsIG5pdHBp
Y2sgYmVsb3cgYW5kIGFsc28geW91DQo+IGRpZG4ndCBpbmNsdWRlIGFsbCB0aGUgZmVlZGJhY2sg
ZnJvbSB0aGUgbGFzdCByb3VuZC4NCj4gDQo+ID4gLS0tDQo+ID4gIGRyaXZlcnMvcGNpL2hvc3Qv
cGNpLWlteDYuYyB8IDE2MQ0KPiA+ICsrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysr
KysrKy0tLS0tDQo+ID4gIDEgZmlsZSBjaGFuZ2VkLCAxNDMgaW5zZXJ0aW9ucygrKSwgMTggZGVs
ZXRpb25zKC0pDQo+ID4NCj4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9wY2kvaG9zdC9wY2ktaW14
Ni5jIGIvZHJpdmVycy9wY2kvaG9zdC9wY2ktaW14Ni5jDQo+ID4gaW5kZXggZWFjOTZmYi4uNWVj
ZTRlMSAxMDA2NDQNCj4gPiAtLS0gYS9kcml2ZXJzL3BjaS9ob3N0L3BjaS1pbXg2LmMNCj4gPiAr
KysgYi9kcml2ZXJzL3BjaS9ob3N0L3BjaS1pbXg2LmMNCj4gPiBAQCAtMjIsOCArMjIsMTAgQEAN
Cj4gPiAgI2luY2x1ZGUgPGxpbnV4L3BjaS5oPg0KPiA+ICAjaW5jbHVkZSA8bGludXgvcGxhdGZv
cm1fZGV2aWNlLmg+DQo+ID4gICNpbmNsdWRlIDxsaW51eC9yZWdtYXAuaD4NCj4gPiArI2luY2x1
ZGUgPGxpbnV4L3JlZ3VsYXRvci9jb25zdW1lci5oPg0KPiA+ICAjaW5jbHVkZSA8bGludXgvcmVz
b3VyY2UuaD4NCj4gPiAgI2luY2x1ZGUgPGxpbnV4L3NpZ25hbC5oPg0KPiA+ICsjaW5jbHVkZSA8
bGludXgvc3lzY29yZV9vcHMuaD4NCj4gPiAgI2luY2x1ZGUgPGxpbnV4L3R5cGVzLmg+DQo+ID4g
ICNpbmNsdWRlIDxsaW51eC9pbnRlcnJ1cHQuaD4NCj4gPg0KPiA+IEBAIC0zNSwxMSArMzcsMTUg
QEAgc3RydWN0IGlteDZfcGNpZSB7DQo+ID4gIAlpbnQJCQlyZXNldF9ncGlvOw0KPiA+ICAJc3Ry
dWN0IGNsawkJKnBjaWVfYnVzOw0KPiA+ICAJc3RydWN0IGNsawkJKnBjaWVfcGh5Ow0KPiA+ICsJ
c3RydWN0IGNsawkJKnBjaWVfaW5ib3VuZF9heGk7DQo+ID4gIAlzdHJ1Y3QgY2xrCQkqcGNpZTsN
Cj4gPiAgCXN0cnVjdCBwY2llX3BvcnQJcHA7DQo+ID4gIAlzdHJ1Y3QgcmVnbWFwCQkqaW9tdXhj
X2dwcjsNCj4gPiArCXN0cnVjdCByZWdtYXAJCSpncGNfaXBzX3JlZzsNCj4gPiArCXN0cnVjdCBy
ZWd1bGF0b3IJKnBjaWVfcGh5X3JlZ3VsYXRvcjsNCj4gPiAgCXZvaWQgX19pb21lbQkJKm1lbV9i
YXNlOw0KPiA+ICB9Ow0KPiA+ICtzdGF0aWMgc3RydWN0IGlteDZfcGNpZSAqaW14Nl9wY2llOw0K
PiANCj4gUmVtb3ZlIHRoaXMgc3RhdGljIHN0cnVjdC4gSSd2ZSBhbHJlYWR5IHNhaWQgb24gdGhl
IGxhc3QgdmVyc2lvbiB0aGF0IHRoaXMgaXMNCj4gY29tcGxldGVseSBiYWNrd2FyZHMuDQo+IA0K
W1JpY2hhcmRdIEkgYWRkZWQgbXkgY29tbWVudHMgaW4gdGhlIGxhc3Qgcm91bmQuDQogQ2FuJ3Qg
dXNlIGlteDZfcGNpZSBzdHJ1Y3Qgc3lzY29yZSBzdXNwZW5kL3Jlc3VtZSwgaWYgdGhlIGlteDZf
cGNpZSBpcyBub3QgYSBzdGF0aWMgdHlwZSBzdHJ1Y3R1cmUuDQoiDQpIaSBMdWNhczoNClJlZ2Fy
ZGluZyB0byB0aGUgZGVmaW5pdGlvbnMocGFzdGVkIGJlbG93KSBvZiB0aGUgc3RydWN0IHN5c2Nv
cmVfb3BzLCBib3RoIHN1c3BlbmQgYW5kIHJlc3VtZSBvZiB0aGUgc3lzY29yZV9vcHMgaXMgdm9p
ZCB0eXBlIGZ1bmN0aW9ucy4NCklmIHRoZXJlIGlzIG5vIHRoZSBzdGF0aWMgZ2xvYmFsIHN0cnVj
dCBpbXg2X3BjaWUsIEkgZG9uJ3Qga25vdyBob3cgaXQgY2FuIGJlIHVzZWQgaW4gc3VzcGVuZC9y
ZXN1bWUgb2YgcGNpX2lteF9zeXNjb3JlX29wcy4NCnN0cnVjdCBzeXNjb3JlX29wcyB7DQogICAg
ICAgIHN0cnVjdCBsaXN0X2hlYWQgbm9kZTsNCiAgICAgICAgaW50ICgqc3VzcGVuZCkodm9pZCk7
DQogICAgICAgIHZvaWQgKCpyZXN1bWUpKHZvaWQpOw0KICAgICAgICB2b2lkICgqc2h1dGRvd24p
KHZvaWQpOw0KfTsNCiINCg0KPiA+DQo+ID4gIC8qIFBDSWUgUm9vdCBDb21wbGV4IHJlZ2lzdGVy
cyAobWVtb3J5LW1hcHBlZCkgKi8NCj4gPiAgI2RlZmluZSBQQ0lFX1JDX0xDUgkJCQkweDdjDQo+
ID4gQEAgLTc3LDYgKzgzLDE4IEBAIHN0cnVjdCBpbXg2X3BjaWUgew0KPiA+ICAjZGVmaW5lIFBI
WV9SWF9PVlJEX0lOX0xPX1JYX0RBVEFfRU4gKDEgPDwgNSkgICNkZWZpbmUNCj4gPiBQSFlfUlhf
T1ZSRF9JTl9MT19SWF9QTExfRU4gKDEgPDwgMykNCj4gPg0KPiA+ICsvKiBHUEMgUENJRSBQSFkg
Yml0IGRlZmluaXRpb25zICovDQo+ID4gKyNkZWZpbmUgR1BDX0NOVFIJCQkwDQo+ID4gKyNkZWZp
bmUgR1BDX0NOVFJfUENJRV9QSFlfUFVQX1JFUQlCSVQoNykNCj4gPiArDQo+ID4gK3N0YXRpYyBp
bmxpbmUgYm9vbCBpc19pbXg2c3hfcGNpZShzdHJ1Y3QgaW14Nl9wY2llICppbXg2X3BjaWUpIHsN
Cj4gPiArCXN0cnVjdCBwY2llX3BvcnQgKnBwID0gJmlteDZfcGNpZS0+cHA7DQo+ID4gKwlzdHJ1
Y3QgZGV2aWNlX25vZGUgKm5wID0gcHAtPmRldi0+b2Zfbm9kZTsNCj4gPiArDQo+ID4gKwlyZXR1
cm4gb2ZfZGV2aWNlX2lzX2NvbXBhdGlibGUobnAsICJmc2wsaW14NnN4LXBjaWUiKTsgfQ0KPiA+
ICsNCj4gPiAgc3RhdGljIGludCBwY2llX3BoeV9wb2xsX2Fjayh2b2lkIF9faW9tZW0gKmRiaV9i
YXNlLCBpbnQgZXhwX3ZhbCkgIHsNCj4gPiAgCXUzMiB2YWw7DQo+ID4gQEAgLTI3NSwxOCArMjkz
LDI5IEBAIHN0YXRpYyBpbnQgaW14Nl9wY2llX2RlYXNzZXJ0X2NvcmVfcmVzZXQoc3RydWN0DQo+
IHBjaWVfcG9ydCAqcHApDQo+ID4gIAkJZ290byBlcnJfcGNpZTsNCj4gPiAgCX0NCj4gPg0KPiA+
IC0JLyogcG93ZXIgdXAgY29yZSBwaHkgYW5kIGVuYWJsZSByZWYgY2xvY2sgKi8NCj4gPiAtCXJl
Z21hcF91cGRhdGVfYml0cyhpbXg2X3BjaWUtPmlvbXV4Y19ncHIsIElPTVVYQ19HUFIxLA0KPiA+
IC0JCQlJTVg2UV9HUFIxX1BDSUVfVEVTVF9QRCwgMCA8PCAxOCk7DQo+ID4gLQkvKg0KPiA+IC0J
ICogdGhlIGFzeW5jIHJlc2V0IGlucHV0IG5lZWQgcmVmIGNsb2NrIHRvIHN5bmMgaW50ZXJuYWxs
eSwNCj4gPiAtCSAqIHdoZW4gdGhlIHJlZiBjbG9jayBjb21lcyBhZnRlciByZXNldCwgaW50ZXJu
YWwgc3luY2VkDQo+ID4gLQkgKiByZXNldCB0aW1lIGlzIHRvbyBzaG9ydCAsIGNhbm5vdCBtZWV0
IHRoZSByZXF1aXJlbWVudC4NCj4gPiAtCSAqIGFkZCBvbmUgfjEwdXMgZGVsYXkgaGVyZS4NCj4g
PiAtCSAqLw0KPiA+IC0JdWRlbGF5KDEwKTsNCj4gPiAtCXJlZ21hcF91cGRhdGVfYml0cyhpbXg2
X3BjaWUtPmlvbXV4Y19ncHIsIElPTVVYQ19HUFIxLA0KPiA+IC0JCQlJTVg2UV9HUFIxX1BDSUVf
UkVGX0NMS19FTiwgMSA8PCAxNik7DQo+ID4gKwlpZiAoaXNfaW14NnN4X3BjaWUoaW14Nl9wY2ll
KSkgew0KPiA+ICsJCXJldCA9IGNsa19wcmVwYXJlX2VuYWJsZShpbXg2X3BjaWUtPnBjaWVfaW5i
b3VuZF9heGkpOw0KPiA+ICsJCWlmIChyZXQpIHsNCj4gPiArCQkJZGV2X2VycihwcC0+ZGV2LCAi
dW5hYmxlIHRvIGVuYWJsZSBwY2llIGNsb2NrXG4iKTsNCj4gPiArCQkJZ290byBlcnJfaW5ib3Vu
ZF9heGk7DQo+ID4gKwkJfQ0KPiA+ICsNCj4gPiArCQlyZWdtYXBfdXBkYXRlX2JpdHMoaW14Nl9w
Y2llLT5pb211eGNfZ3ByLCBJT01VWENfR1BSMTIsDQo+ID4gKwkJCQlJTVg2U1hfR1BSMTJfUENJ
RV9URVNUX1BELCAwKTsNCj4gPiArCX0gZWxzZSB7DQo+ID4gKwkJLyogcG93ZXIgdXAgY29yZSBw
aHkgYW5kIGVuYWJsZSByZWYgY2xvY2sgKi8NCj4gPiArCQlyZWdtYXBfdXBkYXRlX2JpdHMoaW14
Nl9wY2llLT5pb211eGNfZ3ByLCBJT01VWENfR1BSMSwNCj4gPiArCQkJCUlNWDZRX0dQUjFfUENJ
RV9URVNUX1BELCAwKTsNCj4gPiArCQkvKg0KPiA+ICsJCSAqIHRoZSBhc3luYyByZXNldCBpbnB1
dCBuZWVkIHJlZiBjbG9jayB0byBzeW5jIGludGVybmFsbHksDQo+ID4gKwkJICogd2hlbiB0aGUg
cmVmIGNsb2NrIGNvbWVzIGFmdGVyIHJlc2V0LCBpbnRlcm5hbCBzeW5jZWQNCj4gPiArCQkgKiBy
ZXNldCB0aW1lIGlzIHRvbyBzaG9ydCAsIGNhbm5vdCBtZWV0IHRoZSByZXF1aXJlbWVudC4NCj4g
PiArCQkgKiBhZGQgb25lIH4xMHVzIGRlbGF5IGhlcmUuDQo+ID4gKwkJICovDQo+ID4gKwkJdWRl
bGF5KDEwKTsNCj4gPiArCQlyZWdtYXBfdXBkYXRlX2JpdHMoaW14Nl9wY2llLT5pb211eGNfZ3By
LCBJT01VWENfR1BSMSwNCj4gPiArCQkJCUlNWDZRX0dQUjFfUENJRV9SRUZfQ0xLX0VOLCAxIDw8
IDE2KTsNCj4gDQo+IFsuLi5dDQo+IA0KPiBQbGVhc2UgdXNlIElNWDZRX0dQUjFfUENJRV9SRUZf
Q0xLX0VOIGluc3RlYWQgb2YgMSA8PCAxNiBoZXJlLiBJIGtub3cgdGhpcyBpcw0KPiBvbmx5IG1v
dmVkIGNvZGUsIGJ1dCBhcyB5b3UgYXJlIHRvdWNoaW5nIGl0IGFueXdheSB0aGlzIGNsZWFudXAg
c2hvdWxkIGJlDQo+IGZvbGRlZCBpbi4NCltSaWNoYXJkXSBPay4NCj4gDQo+IA0KPiAtLQ0KPiBU
byB1bnN1YnNjcmliZSBmcm9tIHRoaXMgbGlzdDogc2VuZCB0aGUgbGluZSAidW5zdWJzY3JpYmUg
bGludXgtcGNpIiBpbiB0aGUNCj4gYm9keSBvZiBhIG1lc3NhZ2UgdG8gbWFqb3Jkb21vQHZnZXIu
a2VybmVsLm9yZyBNb3JlIG1ham9yZG9tbyBpbmZvIGF0DQo+IGh0dHA6Ly92Z2VyLmtlcm5lbC5v
cmcvbWFqb3Jkb21vLWluZm8uaHRtbA0KDQoNCkJlc3QgUmVnYXJkcw0KUmljaGFyZCBaaHUNCg==

Re: [PATCH v5 4/9] PCI: imx6: add imx6sx pcie support

[Lucas Stach]

Hi Richard,

Am Montag, den 13.10.2014, 02:30 +0000 schrieb
Hong-Xing.Zhu@freescale.com:
> Hi Lucas:
> 
> > -----Original Message-----
> > From: linux-pci-owner@vger.kernel.org [mailto:linux-pci-owner@vger.kernel.org]
> > On Behalf Of Lucas Stach
> > Sent: Sunday, October 12, 2014 10:28 PM
> > To: Richard Zhu
> > Cc: linux-pci@vger.kernel.org; Guo Shawn-R65073; festevam@gmail.com;
> > tharvey@gateworks.com; Zhu Richard-R65037
> > Subject: Re: [PATCH v5 4/9] PCI: imx6: add imx6sx pcie support
> > 
> > Am Freitag, den 10.10.2014, 13:41 +0800 schrieb Richard Zhu:
> > > From: Richard Zhu <r65037@freescale.com>
> > >
> > > - imx6sx pcie has its own standalone pcie power supply.
> > > In order to turn on the imx6sx pcie power during initialization. Add
> > > the pcie regulator and the gpc regmap into the imx6sx pcie structure.
> > > - imx6sx pcie has the new added reset mechanism, add the reset
> > > operations into the initialization.
> > > - Register one PM call-back, enter/exit L2 state of the ASPM during
> > > system suspend/resume.
> > > - disp_axi clock is required by pcie inbound axi port actually.
> > > Add one more clock named pcie_inbound_axi for imx6sx pcie.
> > 
> > > Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
> > 
> > In addition to Fabios comment I have one additional nitpick below and also you
> > didn't include all the feedback from the last round.
> > 
> > > ---
> > >  drivers/pci/host/pci-imx6.c | 161
> > > +++++++++++++++++++++++++++++++++++++++-----
> > >  1 file changed, 143 insertions(+), 18 deletions(-)
> > >
> > > diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
> > > index eac96fb..5ece4e1 100644
> > > --- a/drivers/pci/host/pci-imx6.c
> > > +++ b/drivers/pci/host/pci-imx6.c
> > > @@ -22,8 +22,10 @@
> > >  #include <linux/pci.h>
> > >  #include <linux/platform_device.h>
> > >  #include <linux/regmap.h>
> > > +#include <linux/regulator/consumer.h>
> > >  #include <linux/resource.h>
> > >  #include <linux/signal.h>
> > > +#include <linux/syscore_ops.h>
> > >  #include <linux/types.h>
> > >  #include <linux/interrupt.h>
> > >
> > > @@ -35,11 +37,15 @@ struct imx6_pcie {
> > >  	int			reset_gpio;
> > >  	struct clk		*pcie_bus;
> > >  	struct clk		*pcie_phy;
> > > +	struct clk		*pcie_inbound_axi;
> > >  	struct clk		*pcie;
> > >  	struct pcie_port	pp;
> > >  	struct regmap		*iomuxc_gpr;
> > > +	struct regmap		*gpc_ips_reg;
> > > +	struct regulator	*pcie_phy_regulator;
> > >  	void __iomem		*mem_base;
> > >  };
> > > +static struct imx6_pcie *imx6_pcie;
> > 
> > Remove this static struct. I've already said on the last version that this is
> > completely backwards.
> > 
> [Richard] I added my comments in the last round.
>  Can't use imx6_pcie struct syscore suspend/resume, if the imx6_pcie is not a static type structure.
> "
> Hi Lucas:
> Regarding to the definitions(pasted below) of the struct syscore_ops, both suspend and resume of the syscore_ops is void type functions.
> If there is no the static global struct imx6_pcie, I don't know how it can be used in suspend/resume of pci_imx_syscore_ops.
> struct syscore_ops {
>         struct list_head node;
>         int (*suspend)(void);
>         void (*resume)(void);
>         void (*shutdown)(void);
> };
> "
This only means syscore ops is not the right interface to use here.
Introducing global static vars to hold driver instance state is a
receipt to create trouble later on. Don't ever do this.

I think it should be possible to move those calls to normal dev_pm_ops,
maybe use suspend/resume_noirq or even poweroff/restore_noirq.

Regards,
Lucas

[PATCH v5 5/9] ARM: imx6qdl: enable pcie on imx6qdl sabreauto

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

- enable pcie on imx6qdl sabreauto boards.

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 009abd6..d6040a5 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -410,6 +410,10 @@
 	};
 };
 
+&pcie {
+	status = "okay";
+};
+
 &pwm3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm3>;
-- 
1.9.1

[PATCH v5 6/9] ARM: imx6: update dts and binding for imx6sx pcie

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

- imx6sx pcie phy has its own power regulator. Add the
pcie phy power suppy into im6sx pcie dts and binding.
- in order to align with imx6qdl's pcie dts, re-format
imx6sx pcie dts.
- in order to align with imx6qdl pcie dts format and
keep clean of imx6 pcie driver, keep the pcie phy clock
in imx6sx pcie dts, although it's the parent clk of the
pcie bus clock now, and would be enabled automatically
when pcie bus clock is enabled. secondly, it's
possible that the external osc maybe used as source
of the pcie_bus clk in board design in future.
- disp_axi clock is required by pcie inbound axi port.
Add one more clock named pcie_inbound_axi for imx6sx pcie.

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 .../devicetree/bindings/pci/fsl,imx6q-pcie.txt     |  8 +++++-
 arch/arm/boot/dts/imx6sx.dtsi                      | 32 ++++++++++++----------
 2 files changed, 25 insertions(+), 15 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index 9455fd0..ad81179 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
@@ -4,7 +4,7 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
 and thus inherits all the common properties defined in designware-pcie.txt.
 
 Required properties:
-- compatible: "fsl,imx6q-pcie"
+- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie"
 - reg: base addresse and length of the pcie controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
@@ -13,6 +13,12 @@ Required properties:
 - clock-names: Must include the following additional entries:
 	- "pcie_phy"
 
+Additional required properties for imx6sx-pcie:
+- clock names: Must include the following additional entries:
+	- "pcie_inbound_axi"
+- power supplies:
+	- pcie-phy-supply: regulator used to power the PCIe PHY
+
 Example:
 
 	pcie@0x01000000 {
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index f4b9da6..eefedba 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -599,9 +599,9 @@
 					anatop-max-voltage = <1450000>;
 				};
 
-				reg_pcie: regulator-vddpcie@140 {
+				reg_pcie_phy: regulator-vddpcie-phy@140 {
 					compatible = "fsl,anatop-regulator";
-					regulator-name = "vddpcie";
+					regulator-name = "vddpcie-phy";
 					regulator-min-microvolt = <725000>;
 					regulator-max-microvolt = <1450000>;
 					anatop-reg-offset = <0x140>;
@@ -1184,24 +1184,28 @@
 
 		pcie: pcie@0x08000000 {
 			compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
-			reg = <0x08ffc000 0x4000>; /* DBI */
+			reg = <0x08ffc000 0x4000>, <0x08f00000 0x80000>;
+			reg-names = "rc_dbi", "config";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-				  /* configuration space */
-			ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
-				  /* downstream I/O */
-				  0x81000000 0 0          0x08f80000 0 0x00010000
-				  /* non-prefetchable memory */
-				  0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
+			ranges = <0x81000000 0 0          0x08f80000 0 0x00010000 /* downstream I/O */
+				  0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
 			num-lanes = <1>;
-			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
-				 <&clks IMX6SX_CLK_PCIE_AXI>,
+			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+			                <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+			                <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+			                <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
 				 <&clks IMX6SX_CLK_LVDS1_OUT>,
+				 <&clks IMX6SX_CLK_PCIE_REF_125M>,
 				 <&clks IMX6SX_CLK_DISPLAY_AXI>;
-			clock-names = "pcie_ref_125m", "pcie_axi",
-				      "lvds_gate", "display_axi";
+			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
+			pcie-phy-supply = <&reg_pcie_phy>;
 			status = "disabled";
 		};
 	};
-- 
1.9.1

Re: [PATCH v5 6/9] ARM: imx6: update dts and binding for imx6sx pcie

[Lucas Stach]

Am Freitag, den 10.10.2014, 13:41 +0800 schrieb Richard Zhu:
> From: Richard Zhu <r65037@freescale.com>
> 
> - imx6sx pcie phy has its own power regulator. Add the
> pcie phy power suppy into im6sx pcie dts and binding.
> - in order to align with imx6qdl's pcie dts, re-format
> imx6sx pcie dts.
> - in order to align with imx6qdl pcie dts format and
> keep clean of imx6 pcie driver, keep the pcie phy clock
> in imx6sx pcie dts, although it's the parent clk of the
> pcie bus clock now, and would be enabled automatically
> when pcie bus clock is enabled. secondly, it's
> possible that the external osc maybe used as source
> of the pcie_bus clk in board design in future.
> - disp_axi clock is required by pcie inbound axi port.
> Add one more clock named pcie_inbound_axi for imx6sx pcie.
> 
> Signed-off-by: Richard Zhu <richard.zhu@freescale.com>

One nit below, otherwise this looks fine now.

> ---
>  .../devicetree/bindings/pci/fsl,imx6q-pcie.txt     |  8 +++++-
>  arch/arm/boot/dts/imx6sx.dtsi                      | 32 ++++++++++++----------
>  2 files changed, 25 insertions(+), 15 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> index 9455fd0..ad81179 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> @@ -4,7 +4,7 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
>  and thus inherits all the common properties defined in designware-pcie.txt.
>  
>  Required properties:
> -- compatible: "fsl,imx6q-pcie"
> +- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie"
>  - reg: base addresse and length of the pcie controller
>  - interrupts: A list of interrupt outputs of the controller. Must contain an
>    entry for each entry in the interrupt-names property.
> @@ -13,6 +13,12 @@ Required properties:
>  - clock-names: Must include the following additional entries:
>  	- "pcie_phy"
>  
> +Additional required properties for imx6sx-pcie:
> +- clock names: Must include the following additional entries:
> +	- "pcie_inbound_axi"
> +- power supplies:
> +	- pcie-phy-supply: regulator used to power the PCIe PHY
> +
>  Example:
>  
>  	pcie@0x01000000 {
> diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
> index f4b9da6..eefedba 100644
> --- a/arch/arm/boot/dts/imx6sx.dtsi
> +++ b/arch/arm/boot/dts/imx6sx.dtsi
> @@ -599,9 +599,9 @@
>  					anatop-max-voltage = <1450000>;
>  				};
>  
> -				reg_pcie: regulator-vddpcie@140 {
> +				reg_pcie_phy: regulator-vddpcie-phy@140 {
>  					compatible = "fsl,anatop-regulator";
> -					regulator-name = "vddpcie";
> +					regulator-name = "vddpcie-phy";
>  					regulator-min-microvolt = <725000>;
>  					regulator-max-microvolt = <1450000>;
>  					anatop-reg-offset = <0x140>;
> @@ -1184,24 +1184,28 @@
>  
>  		pcie: pcie@0x08000000 {
>  			compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
> -			reg = <0x08ffc000 0x4000>; /* DBI */
> +			reg = <0x08ffc000 0x4000>, <0x08f00000 0x80000>;
> +			reg-names = "rc_dbi", "config";

While it doesn't make a fucntional change, I would like to see this
aligned to imx6q, which means the first reg name is just "dbi".
 
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			device_type = "pci";
> -				  /* configuration space */
> -			ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
> -				  /* downstream I/O */
> -				  0x81000000 0 0          0x08f80000 0 0x00010000
> -				  /* non-prefetchable memory */
> -				  0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
> +			ranges = <0x81000000 0 0          0x08f80000 0 0x00010000 /* downstream I/O */
> +				  0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
>  			num-lanes = <1>;
> -			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
> -				 <&clks IMX6SX_CLK_PCIE_AXI>,
> +			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "msi";
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 0x7>;
> +			interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> +			                <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
> +			                <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
> +			                <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
>  				 <&clks IMX6SX_CLK_LVDS1_OUT>,
> +				 <&clks IMX6SX_CLK_PCIE_REF_125M>,
>  				 <&clks IMX6SX_CLK_DISPLAY_AXI>;
> -			clock-names = "pcie_ref_125m", "pcie_axi",
> -				      "lvds_gate", "display_axi";
> +			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
> +			pcie-phy-supply = <&reg_pcie_phy>;
>  			status = "disabled";
>  		};
>  	};

RE: [PATCH v5 6/9] ARM: imx6: update dts and binding for imx6sx pcie

[Hong-Xing.Zhu]

DQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IGxpbnV4LXBjaS1vd25lckB2
Z2VyLmtlcm5lbC5vcmcgW21haWx0bzpsaW51eC1wY2ktb3duZXJAdmdlci5rZXJuZWwub3JnXQ0K
PiBPbiBCZWhhbGYgT2YgTHVjYXMgU3RhY2gNCj4gU2VudDogU3VuZGF5LCBPY3RvYmVyIDEyLCAy
MDE0IDEwOjM1IFBNDQo+IFRvOiBSaWNoYXJkIFpodQ0KPiBDYzogbGludXgtcGNpQHZnZXIua2Vy
bmVsLm9yZzsgR3VvIFNoYXduLVI2NTA3MzsgZmVzdGV2YW1AZ21haWwuY29tOw0KPiB0aGFydmV5
QGdhdGV3b3Jrcy5jb207IFpodSBSaWNoYXJkLVI2NTAzNw0KPiBTdWJqZWN0OiBSZTogW1BBVENI
IHY1IDYvOV0gQVJNOiBpbXg2OiB1cGRhdGUgZHRzIGFuZCBiaW5kaW5nIGZvciBpbXg2c3ggcGNp
ZQ0KPiANCj4gQW0gRnJlaXRhZywgZGVuIDEwLjEwLjIwMTQsIDEzOjQxICswODAwIHNjaHJpZWIg
UmljaGFyZCBaaHU6DQo+ID4gRnJvbTogUmljaGFyZCBaaHUgPHI2NTAzN0BmcmVlc2NhbGUuY29t
Pg0KPiA+DQo+ID4gLSBpbXg2c3ggcGNpZSBwaHkgaGFzIGl0cyBvd24gcG93ZXIgcmVndWxhdG9y
LiBBZGQgdGhlIHBjaWUgcGh5IHBvd2VyDQo+ID4gc3VwcHkgaW50byBpbTZzeCBwY2llIGR0cyBh
bmQgYmluZGluZy4NCj4gPiAtIGluIG9yZGVyIHRvIGFsaWduIHdpdGggaW14NnFkbCdzIHBjaWUg
ZHRzLCByZS1mb3JtYXQgaW14NnN4IHBjaWUNCj4gPiBkdHMuDQo+ID4gLSBpbiBvcmRlciB0byBh
bGlnbiB3aXRoIGlteDZxZGwgcGNpZSBkdHMgZm9ybWF0IGFuZCBrZWVwIGNsZWFuIG9mDQo+ID4g
aW14NiBwY2llIGRyaXZlciwga2VlcCB0aGUgcGNpZSBwaHkgY2xvY2sgaW4gaW14NnN4IHBjaWUg
ZHRzLCBhbHRob3VnaA0KPiA+IGl0J3MgdGhlIHBhcmVudCBjbGsgb2YgdGhlIHBjaWUgYnVzIGNs
b2NrIG5vdywgYW5kIHdvdWxkIGJlIGVuYWJsZWQNCj4gPiBhdXRvbWF0aWNhbGx5IHdoZW4gcGNp
ZSBidXMgY2xvY2sgaXMgZW5hYmxlZC4gc2Vjb25kbHksIGl0J3MgcG9zc2libGUNCj4gPiB0aGF0
IHRoZSBleHRlcm5hbCBvc2MgbWF5YmUgdXNlZCBhcyBzb3VyY2Ugb2YgdGhlIHBjaWVfYnVzIGNs
ayBpbg0KPiA+IGJvYXJkIGRlc2lnbiBpbiBmdXR1cmUuDQo+ID4gLSBkaXNwX2F4aSBjbG9jayBp
cyByZXF1aXJlZCBieSBwY2llIGluYm91bmQgYXhpIHBvcnQuDQo+ID4gQWRkIG9uZSBtb3JlIGNs
b2NrIG5hbWVkIHBjaWVfaW5ib3VuZF9heGkgZm9yIGlteDZzeCBwY2llLg0KPiA+DQo+ID4gU2ln
bmVkLW9mZi1ieTogUmljaGFyZCBaaHUgPHJpY2hhcmQuemh1QGZyZWVzY2FsZS5jb20+DQo+IA0K
PiBPbmUgbml0IGJlbG93LCBvdGhlcndpc2UgdGhpcyBsb29rcyBmaW5lIG5vdy4NCj4gDQo+ID4g
LS0tDQo+ID4gIC4uLi9kZXZpY2V0cmVlL2JpbmRpbmdzL3BjaS9mc2wsaW14NnEtcGNpZS50eHQg
ICAgIHwgIDggKysrKystDQo+ID4gIGFyY2gvYXJtL2Jvb3QvZHRzL2lteDZzeC5kdHNpICAgICAg
ICAgICAgICAgICAgICAgIHwgMzIgKysrKysrKysrKysrLS0tLS0tLQ0KPiAtLS0NCj4gPiAgMiBm
aWxlcyBjaGFuZ2VkLCAyNSBpbnNlcnRpb25zKCspLCAxNSBkZWxldGlvbnMoLSkNCj4gPg0KPiA+
IGRpZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvcGNpL2ZzbCxp
bXg2cS1wY2llLnR4dA0KPiA+IGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL3Bj
aS9mc2wsaW14NnEtcGNpZS50eHQNCj4gPiBpbmRleCA5NDU1ZmQwLi5hZDgxMTc5IDEwMDY0NA0K
PiA+IC0tLSBhL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9wY2kvZnNsLGlteDZx
LXBjaWUudHh0DQo+ID4gKysrIGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL3Bj
aS9mc2wsaW14NnEtcGNpZS50eHQNCj4gPiBAQCAtNCw3ICs0LDcgQEAgVGhpcyBQQ0llIGhvc3Qg
Y29udHJvbGxlciBpcyBiYXNlZCBvbiB0aGUgU3lub3BzaXMNCj4gPiBEZXNpZ253YXJlIFBDSWUg
SVAgIGFuZCB0aHVzIGluaGVyaXRzIGFsbCB0aGUgY29tbW9uIHByb3BlcnRpZXMgZGVmaW5lZCBp
bg0KPiBkZXNpZ253YXJlLXBjaWUudHh0Lg0KPiA+DQo+ID4gIFJlcXVpcmVkIHByb3BlcnRpZXM6
DQo+ID4gLS0gY29tcGF0aWJsZTogImZzbCxpbXg2cS1wY2llIg0KPiA+ICstIGNvbXBhdGlibGU6
ICJmc2wsaW14NnEtcGNpZSIsICJmc2wsaW14NnN4LXBjaWUiDQo+ID4gIC0gcmVnOiBiYXNlIGFk
ZHJlc3NlIGFuZCBsZW5ndGggb2YgdGhlIHBjaWUgY29udHJvbGxlcg0KPiA+ICAtIGludGVycnVw
dHM6IEEgbGlzdCBvZiBpbnRlcnJ1cHQgb3V0cHV0cyBvZiB0aGUgY29udHJvbGxlci4gTXVzdCBj
b250YWluDQo+IGFuDQo+ID4gICAgZW50cnkgZm9yIGVhY2ggZW50cnkgaW4gdGhlIGludGVycnVw
dC1uYW1lcyBwcm9wZXJ0eS4NCj4gPiBAQCAtMTMsNiArMTMsMTIgQEAgUmVxdWlyZWQgcHJvcGVy
dGllczoNCj4gPiAgLSBjbG9jay1uYW1lczogTXVzdCBpbmNsdWRlIHRoZSBmb2xsb3dpbmcgYWRk
aXRpb25hbCBlbnRyaWVzOg0KPiA+ICAJLSAicGNpZV9waHkiDQo+ID4NCj4gPiArQWRkaXRpb25h
bCByZXF1aXJlZCBwcm9wZXJ0aWVzIGZvciBpbXg2c3gtcGNpZToNCj4gPiArLSBjbG9jayBuYW1l
czogTXVzdCBpbmNsdWRlIHRoZSBmb2xsb3dpbmcgYWRkaXRpb25hbCBlbnRyaWVzOg0KPiA+ICsJ
LSAicGNpZV9pbmJvdW5kX2F4aSINCj4gPiArLSBwb3dlciBzdXBwbGllczoNCj4gPiArCS0gcGNp
ZS1waHktc3VwcGx5OiByZWd1bGF0b3IgdXNlZCB0byBwb3dlciB0aGUgUENJZSBQSFkNCj4gPiAr
DQo+ID4gIEV4YW1wbGU6DQo+ID4NCj4gPiAgCXBjaWVAMHgwMTAwMDAwMCB7DQo+ID4gZGlmZiAt
LWdpdCBhL2FyY2gvYXJtL2Jvb3QvZHRzL2lteDZzeC5kdHNpDQo+ID4gYi9hcmNoL2FybS9ib290
L2R0cy9pbXg2c3guZHRzaSBpbmRleCBmNGI5ZGE2Li5lZWZlZGJhIDEwMDY0NA0KPiA+IC0tLSBh
L2FyY2gvYXJtL2Jvb3QvZHRzL2lteDZzeC5kdHNpDQo+ID4gKysrIGIvYXJjaC9hcm0vYm9vdC9k
dHMvaW14NnN4LmR0c2kNCj4gPiBAQCAtNTk5LDkgKzU5OSw5IEBADQo+ID4gIAkJCQkJYW5hdG9w
LW1heC12b2x0YWdlID0gPDE0NTAwMDA+Ow0KPiA+ICAJCQkJfTsNCj4gPg0KPiA+IC0JCQkJcmVn
X3BjaWU6IHJlZ3VsYXRvci12ZGRwY2llQDE0MCB7DQo+ID4gKwkJCQlyZWdfcGNpZV9waHk6IHJl
Z3VsYXRvci12ZGRwY2llLXBoeUAxNDAgew0KPiA+ICAJCQkJCWNvbXBhdGlibGUgPSAiZnNsLGFu
YXRvcC1yZWd1bGF0b3IiOw0KPiA+IC0JCQkJCXJlZ3VsYXRvci1uYW1lID0gInZkZHBjaWUiOw0K
PiA+ICsJCQkJCXJlZ3VsYXRvci1uYW1lID0gInZkZHBjaWUtcGh5IjsNCj4gPiAgCQkJCQlyZWd1
bGF0b3ItbWluLW1pY3Jvdm9sdCA9IDw3MjUwMDA+Ow0KPiA+ICAJCQkJCXJlZ3VsYXRvci1tYXgt
bWljcm92b2x0ID0gPDE0NTAwMDA+Ow0KPiA+ICAJCQkJCWFuYXRvcC1yZWctb2Zmc2V0ID0gPDB4
MTQwPjsNCj4gPiBAQCAtMTE4NCwyNCArMTE4NCwyOCBAQA0KPiA+DQo+ID4gIAkJcGNpZTogcGNp
ZUAweDA4MDAwMDAwIHsNCj4gPiAgCQkJY29tcGF0aWJsZSA9ICJmc2wsaW14NnN4LXBjaWUiLCAi
c25wcyxkdy1wY2llIjsNCj4gPiAtCQkJcmVnID0gPDB4MDhmZmMwMDAgMHg0MDAwPjsgLyogREJJ
ICovDQo+ID4gKwkJCXJlZyA9IDwweDA4ZmZjMDAwIDB4NDAwMD4sIDwweDA4ZjAwMDAwIDB4ODAw
MDA+Ow0KPiA+ICsJCQlyZWctbmFtZXMgPSAicmNfZGJpIiwgImNvbmZpZyI7DQo+IA0KPiBXaGls
ZSBpdCBkb2Vzbid0IG1ha2UgYSBmdWNudGlvbmFsIGNoYW5nZSwgSSB3b3VsZCBsaWtlIHRvIHNl
ZSB0aGlzIGFsaWduZWQgdG8NCj4gaW14NnEsIHdoaWNoIG1lYW5zIHRoZSBmaXJzdCByZWcgbmFt
ZSBpcyBqdXN0ICJkYmkiLg0KPiANCltSaWNoYXJkXSBUaGFua3MgZm9yIHlvdXIga2luZGx5IHJl
dmlldy4NClRoZSBuYW1lIHdvdWxkIGJlIGNoYW5nZWQgZnJvbSAicmNfZGJpIiB0byAiZGJpIiwg
dGhhbmtzLg0KDQo+ID4gIAkJCSNhZGRyZXNzLWNlbGxzID0gPDM+Ow0KPiA+ICAJCQkjc2l6ZS1j
ZWxscyA9IDwyPjsNCj4gPiAgCQkJZGV2aWNlX3R5cGUgPSAicGNpIjsNCj4gPiAtCQkJCSAgLyog
Y29uZmlndXJhdGlvbiBzcGFjZSAqLw0KPiA+IC0JCQlyYW5nZXMgPSA8MHgwMDAwMDgwMCAwIDB4
MDhmMDAwMDAgMHgwOGYwMDAwMCAwIDB4MDAwODAwMDANCj4gPiAtCQkJCSAgLyogZG93bnN0cmVh
bSBJL08gKi8NCj4gPiAtCQkJCSAgMHg4MTAwMDAwMCAwIDAgICAgICAgICAgMHgwOGY4MDAwMCAw
IDB4MDAwMTAwMDANCj4gPiAtCQkJCSAgLyogbm9uLXByZWZldGNoYWJsZSBtZW1vcnkgKi8NCj4g
PiAtCQkJCSAgMHg4MjAwMDAwMCAwIDB4MDgwMDAwMDAgMHgwODAwMDAwMCAwIDB4MDBmMDAwMDA+
Ow0KPiA+ICsJCQlyYW5nZXMgPSA8MHg4MTAwMDAwMCAwIDAgICAgICAgICAgMHgwOGY4MDAwMCAw
IDB4MDAwMTAwMDAgLyoNCj4gZG93bnN0cmVhbSBJL08gKi8NCj4gPiArCQkJCSAgMHg4MjAwMDAw
MCAwIDB4MDgwMDAwMDAgMHgwODAwMDAwMCAwIDB4MDBmMDAwMDA+OyAvKg0KPiA+ICtub24tcHJl
ZmV0Y2hhYmxlIG1lbW9yeSAqLw0KPiA+ICAJCQludW0tbGFuZXMgPSA8MT47DQo+ID4gLQkJCWlu
dGVycnVwdHMgPSA8R0lDX1NQSSAxMjMgSVJRX1RZUEVfTEVWRUxfSElHSD47DQo+ID4gLQkJCWNs
b2NrcyA9IDwmY2xrcyBJTVg2U1hfQ0xLX1BDSUVfUkVGXzEyNU0+LA0KPiA+IC0JCQkJIDwmY2xr
cyBJTVg2U1hfQ0xLX1BDSUVfQVhJPiwNCj4gPiArCQkJaW50ZXJydXB0cyA9IDxHSUNfU1BJIDEy
MCBJUlFfVFlQRV9MRVZFTF9ISUdIPjsNCj4gPiArCQkJaW50ZXJydXB0LW5hbWVzID0gIm1zaSI7
DQo+ID4gKwkJCSNpbnRlcnJ1cHQtY2VsbHMgPSA8MT47DQo+ID4gKwkJCWludGVycnVwdC1tYXAt
bWFzayA9IDwwIDAgMCAweDc+Ow0KPiA+ICsJCQlpbnRlcnJ1cHQtbWFwID0gPDAgMCAwIDEgJmlu
dGMgR0lDX1NQSSAxMjMgSVJRX1RZUEVfTEVWRUxfSElHSD4sDQo+ID4gKwkJCSAgICAgICAgICAg
ICAgICA8MCAwIDAgMiAmaW50YyBHSUNfU1BJIDEyMiBJUlFfVFlQRV9MRVZFTF9ISUdIPiwNCj4g
PiArCQkJICAgICAgICAgICAgICAgIDwwIDAgMCAzICZpbnRjIEdJQ19TUEkgMTIxIElSUV9UWVBF
X0xFVkVMX0hJR0g+LA0KPiA+ICsJCQkgICAgICAgICAgICAgICAgPDAgMCAwIDQgJmludGMgR0lD
X1NQSSAxMjAgSVJRX1RZUEVfTEVWRUxfSElHSD47DQo+ID4gKwkJCWNsb2NrcyA9IDwmY2xrcyBJ
TVg2U1hfQ0xLX1BDSUVfQVhJPiwNCj4gPiAgCQkJCSA8JmNsa3MgSU1YNlNYX0NMS19MVkRTMV9P
VVQ+LA0KPiA+ICsJCQkJIDwmY2xrcyBJTVg2U1hfQ0xLX1BDSUVfUkVGXzEyNU0+LA0KPiA+ICAJ
CQkJIDwmY2xrcyBJTVg2U1hfQ0xLX0RJU1BMQVlfQVhJPjsNCj4gPiAtCQkJY2xvY2stbmFtZXMg
PSAicGNpZV9yZWZfMTI1bSIsICJwY2llX2F4aSIsDQo+ID4gLQkJCQkgICAgICAibHZkc19nYXRl
IiwgImRpc3BsYXlfYXhpIjsNCj4gPiArCQkJY2xvY2stbmFtZXMgPSAicGNpZSIsICJwY2llX2J1
cyIsICJwY2llX3BoeSIsDQo+ICJwY2llX2luYm91bmRfYXhpIjsNCj4gPiArCQkJcGNpZS1waHkt
c3VwcGx5ID0gPCZyZWdfcGNpZV9waHk+Ow0KPiA+ICAJCQlzdGF0dXMgPSAiZGlzYWJsZWQiOw0K
PiA+ICAJCX07DQo+ID4gIAl9Ow0KPiANCj4gDQo+IC0tDQo+IFRvIHVuc3Vic2NyaWJlIGZyb20g
dGhpcyBsaXN0OiBzZW5kIHRoZSBsaW5lICJ1bnN1YnNjcmliZSBsaW51eC1wY2kiIGluIHRoZQ0K
PiBib2R5IG9mIGEgbWVzc2FnZSB0byBtYWpvcmRvbW9Admdlci5rZXJuZWwub3JnIE1vcmUgbWFq
b3Jkb21vIGluZm8gYXQNCj4gaHR0cDovL3ZnZXIua2VybmVsLm9yZy9tYWpvcmRvbW8taW5mby5o
dG1sDQoNCg0KQmVzdCBSZWdhcmRzDQpSaWNoYXJkIFpodQ0KDQo=

[PATCH v5 7/9] ARM: imx6sx: add syscon into gpc dts

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

In order to manipulate gpc bits for imx6sx
pcie in driver, add syscon into gpc dts

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 arch/arm/boot/dts/imx6sx.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index eefedba..0c3822e 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -689,7 +689,8 @@
 			};
 
 			gpc: gpc@020dc000 {
-				compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
+				compatible = "fsl,imx6sx-gpc",
+					     "fsl,imx6q-gpc", "syscon";
 				reg = <0x020dc000 0x4000>;
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 			};
-- 
1.9.1

[PATCH v5 8/9] ARM: imx6sx: add imx6sx pcie related gpr bits definitions

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index ff44374..3273b87 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -301,6 +301,7 @@
 #define IMX6Q_GPR12_DEVICE_TYPE			(0xf << 12)
 #define IMX6Q_GPR12_PCIE_CTL_2			BIT(10)
 #define IMX6Q_GPR12_LOS_LEVEL			(0x1f << 4)
+#define IMX6Q_GPR12_LOS_LEVEL_9			(0x9 << 4)
 
 #define IMX6Q_GPR13_SDMA_STOP_REQ		BIT(30)
 #define IMX6Q_GPR13_CAN2_STOP_REQ		BIT(29)
@@ -395,4 +396,12 @@
 #define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK    (0x3 << 17)
 #define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK    (0x1 << 14)
 
+/* For imx6sx iomux gpr register field define */
+#define IMX6SX_GPR5_PCIE_BTNRST			BIT(19)
+#define IMX6SX_GPR5_PCIE_PERST			BIT(18)
+
+#define IMX6SX_GPR12_PCIE_PM_TURN_OFF		BIT(16)
+#define IMX6SX_GPR12_PCIE_TEST_PD		BIT(30)
+#define IMX6SX_GPR12_RX_EQ_MASK			(0x7 << 0)
+#define IMX6SX_GPR12_RX_EQ_2			(0x2 << 0)
 #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
-- 
1.9.1

Re: [PATCH v5 8/9] ARM: imx6sx: add imx6sx pcie related gpr bits definitions

[Lucas Stach]

Am Freitag, den 10.10.2014, 13:41 +0800 schrieb Richard Zhu:
> From: Richard Zhu <r65037@freescale.com>
> 
> Signed-off-by: Richard Zhu <richard.zhu@freescale.com>

You are using those defines in the PCIe driver changes, so the need to
be sorted before them in the series as they need to be picked up by
Bjorn to make sure we don't introduce build regressions.

> ---
>  include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
> index ff44374..3273b87 100644
> --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
> +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
> @@ -301,6 +301,7 @@
>  #define IMX6Q_GPR12_DEVICE_TYPE			(0xf << 12)
>  #define IMX6Q_GPR12_PCIE_CTL_2			BIT(10)
>  #define IMX6Q_GPR12_LOS_LEVEL			(0x1f << 4)
> +#define IMX6Q_GPR12_LOS_LEVEL_9			(0x9 << 4)
>  
>  #define IMX6Q_GPR13_SDMA_STOP_REQ		BIT(30)
>  #define IMX6Q_GPR13_CAN2_STOP_REQ		BIT(29)
> @@ -395,4 +396,12 @@
>  #define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK    (0x3 << 17)
>  #define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK    (0x1 << 14)
>  
> +/* For imx6sx iomux gpr register field define */
> +#define IMX6SX_GPR5_PCIE_BTNRST			BIT(19)
> +#define IMX6SX_GPR5_PCIE_PERST			BIT(18)
> +
> +#define IMX6SX_GPR12_PCIE_PM_TURN_OFF		BIT(16)
> +#define IMX6SX_GPR12_PCIE_TEST_PD		BIT(30)
> +#define IMX6SX_GPR12_RX_EQ_MASK			(0x7 << 0)
> +#define IMX6SX_GPR12_RX_EQ_2			(0x2 << 0)
>  #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */

RE: [PATCH v5 8/9] ARM: imx6sx: add imx6sx pcie related gpr bits definitions

[Hong-Xing.Zhu]

DQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IGxpbnV4LXBjaS1vd25lckB2
Z2VyLmtlcm5lbC5vcmcgW21haWx0bzpsaW51eC1wY2ktb3duZXJAdmdlci5rZXJuZWwub3JnXQ0K
PiBPbiBCZWhhbGYgT2YgTHVjYXMgU3RhY2gNCj4gU2VudDogU3VuZGF5LCBPY3RvYmVyIDEyLCAy
MDE0IDEwOjM4IFBNDQo+IFRvOiBSaWNoYXJkIFpodQ0KPiBDYzogbGludXgtcGNpQHZnZXIua2Vy
bmVsLm9yZzsgR3VvIFNoYXduLVI2NTA3MzsgZmVzdGV2YW1AZ21haWwuY29tOw0KPiB0aGFydmV5
QGdhdGV3b3Jrcy5jb207IFpodSBSaWNoYXJkLVI2NTAzNw0KPiBTdWJqZWN0OiBSZTogW1BBVENI
IHY1IDgvOV0gQVJNOiBpbXg2c3g6IGFkZCBpbXg2c3ggcGNpZSByZWxhdGVkIGdwciBiaXRzDQo+
IGRlZmluaXRpb25zDQo+IA0KPiBBbSBGcmVpdGFnLCBkZW4gMTAuMTAuMjAxNCwgMTM6NDEgKzA4
MDAgc2NocmllYiBSaWNoYXJkIFpodToNCj4gPiBGcm9tOiBSaWNoYXJkIFpodSA8cjY1MDM3QGZy
ZWVzY2FsZS5jb20+DQo+ID4NCj4gPiBTaWduZWQtb2ZmLWJ5OiBSaWNoYXJkIFpodSA8cmljaGFy
ZC56aHVAZnJlZXNjYWxlLmNvbT4NCj4gDQo+IFlvdSBhcmUgdXNpbmcgdGhvc2UgZGVmaW5lcyBp
biB0aGUgUENJZSBkcml2ZXIgY2hhbmdlcywgc28gdGhlIG5lZWQgdG8gYmUNCj4gc29ydGVkIGJl
Zm9yZSB0aGVtIGluIHRoZSBzZXJpZXMgYXMgdGhleSBuZWVkIHRvIGJlIHBpY2tlZCB1cCBieSBC
am9ybiB0byBtYWtlDQo+IHN1cmUgd2UgZG9uJ3QgaW50cm9kdWNlIGJ1aWxkIHJlZ3Jlc3Npb25z
Lg0KPiANCltSaWNoYXJkXSBUaGFua3MgZm9yIHlvdXIga2luZGx5IHJldmlldy4NCk9rLCB3b3Vs
ZCBiZSBwbGFjZWQganVzdCBiZWhpbmQgdGhlIG1vZGlmaWNhdGlvbnMgb2YgdGhlIGRlc2lnbi13
YXJlIGNvZGVzLg0KDQo+ID4gLS0tDQo+ID4gIGluY2x1ZGUvbGludXgvbWZkL3N5c2Nvbi9pbXg2
cS1pb211eGMtZ3ByLmggfCA5ICsrKysrKysrKw0KPiA+ICAxIGZpbGUgY2hhbmdlZCwgOSBpbnNl
cnRpb25zKCspDQo+ID4NCj4gPiBkaWZmIC0tZ2l0IGEvaW5jbHVkZS9saW51eC9tZmQvc3lzY29u
L2lteDZxLWlvbXV4Yy1ncHIuaA0KPiA+IGIvaW5jbHVkZS9saW51eC9tZmQvc3lzY29uL2lteDZx
LWlvbXV4Yy1ncHIuaA0KPiA+IGluZGV4IGZmNDQzNzQuLjMyNzNiODcgMTAwNjQ0DQo+ID4gLS0t
IGEvaW5jbHVkZS9saW51eC9tZmQvc3lzY29uL2lteDZxLWlvbXV4Yy1ncHIuaA0KPiA+ICsrKyBi
L2luY2x1ZGUvbGludXgvbWZkL3N5c2Nvbi9pbXg2cS1pb211eGMtZ3ByLmgNCj4gPiBAQCAtMzAx
LDYgKzMwMSw3IEBADQo+ID4gICNkZWZpbmUgSU1YNlFfR1BSMTJfREVWSUNFX1RZUEUJCQkoMHhm
IDw8IDEyKQ0KPiA+ICAjZGVmaW5lIElNWDZRX0dQUjEyX1BDSUVfQ1RMXzIJCQlCSVQoMTApDQo+
ID4gICNkZWZpbmUgSU1YNlFfR1BSMTJfTE9TX0xFVkVMCQkJKDB4MWYgPDwgNCkNCj4gPiArI2Rl
ZmluZSBJTVg2UV9HUFIxMl9MT1NfTEVWRUxfOQkJCSgweDkgPDwgNCkNCj4gPg0KPiA+ICAjZGVm
aW5lIElNWDZRX0dQUjEzX1NETUFfU1RPUF9SRVEJCUJJVCgzMCkNCj4gPiAgI2RlZmluZSBJTVg2
UV9HUFIxM19DQU4yX1NUT1BfUkVRCQlCSVQoMjkpDQo+ID4gQEAgLTM5NSw0ICszOTYsMTIgQEAN
Cj4gPiAgI2RlZmluZSBJTVg2U0xfR1BSMV9GRUNfQ0xPQ0tfTVVYMV9TRUxfTUFTSyAgICAoMHgz
IDw8IDE3KQ0KPiA+ICAjZGVmaW5lIElNWDZTTF9HUFIxX0ZFQ19DTE9DS19NVVgyX1NFTF9NQVNL
ICAgICgweDEgPDwgMTQpDQo+ID4NCj4gPiArLyogRm9yIGlteDZzeCBpb211eCBncHIgcmVnaXN0
ZXIgZmllbGQgZGVmaW5lICovDQo+ID4gKyNkZWZpbmUgSU1YNlNYX0dQUjVfUENJRV9CVE5SU1QJ
CQlCSVQoMTkpDQo+ID4gKyNkZWZpbmUgSU1YNlNYX0dQUjVfUENJRV9QRVJTVAkJCUJJVCgxOCkN
Cj4gPiArDQo+ID4gKyNkZWZpbmUgSU1YNlNYX0dQUjEyX1BDSUVfUE1fVFVSTl9PRkYJCUJJVCgx
NikNCj4gPiArI2RlZmluZSBJTVg2U1hfR1BSMTJfUENJRV9URVNUX1BECQlCSVQoMzApDQo+ID4g
KyNkZWZpbmUgSU1YNlNYX0dQUjEyX1JYX0VRX01BU0sJCQkoMHg3IDw8IDApDQo+ID4gKyNkZWZp
bmUgSU1YNlNYX0dQUjEyX1JYX0VRXzIJCQkoMHgyIDw8IDApDQo+ID4gICNlbmRpZiAvKiBfX0xJ
TlVYX0lNWDZRX0lPTVVYQ19HUFJfSCAqLw0KPiANCj4gDQo+IC0tDQo+IFRvIHVuc3Vic2NyaWJl
IGZyb20gdGhpcyBsaXN0OiBzZW5kIHRoZSBsaW5lICJ1bnN1YnNjcmliZSBsaW51eC1wY2kiIGlu
IHRoZQ0KPiBib2R5IG9mIGEgbWVzc2FnZSB0byBtYWpvcmRvbW9Admdlci5rZXJuZWwub3JnIE1v
cmUgbWFqb3Jkb21vIGluZm8gYXQNCj4gaHR0cDovL3ZnZXIua2VybmVsLm9yZy9tYWpvcmRvbW8t
aW5mby5odG1sDQoNCkJlc3QgUmVnYXJkcw0KUmljaGFyZCBaaHUNCg==

[PATCH v5 9/9] ARM: imx6sx: enable pcie on imx6sx sdb board

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 arch/arm/boot/dts/imx6sx-sdb.dts | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index a3980d9..e538ceb 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -90,6 +90,19 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 		};
+
+		reg_pcie: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_pcie_reg>;
+			regulator-name = "MPCIE_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio2 1 0>;
+			regulator-always-on;
+			enable-active-high;
+		};
 	};
 
 	sound {
@@ -251,6 +264,13 @@
 	};
 };
 
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio2 0 0>;
+	status = "okay";
+};
+
 &ssi2 {
 	status = "okay";
 };
@@ -365,6 +385,18 @@
 			>;
 		};
 
+		pinctrl_pcie: pciegrp {
+			fsl,pins = <
+				MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x17059
+			>;
+		};
+
+		pinctrl_pcie_reg: pciereggrp {
+			fsl,pins = <
+				MX6SX_PAD_ENET1_CRS__GPIO2_IO_1	0x17059
+			>;
+		};
+
 		pinctrl_vcc_sd3: vccsd3grp {
 			fsl,pins = <
 				MX6SX_PAD_KEY_COL1__GPIO2_IO_11		0x17059
-- 
1.9.1

Re: [PATCH v5 9/9] ARM: imx6sx: enable pcie on imx6sx sdb board

[Fabio Estevam]

On Fri, Oct 10, 2014 at 2:41 AM, Richard Zhu <richard.zhu@freescale.com> wrote:

> +               pinctrl_pcie: pciegrp {
> +                       fsl,pins = <
> +                               MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x17059

Why 0x17059 instead of the default 0x10b0?

> +                       >;
> +               };
> +
> +               pinctrl_pcie_reg: pciereggrp {
> +                       fsl,pins = <
> +                               MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x17059

Same here.

RE: [PATCH v5 9/9] ARM: imx6sx: enable pcie on imx6sx sdb board

[Hong-Xing.Zhu]

DQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IEZhYmlvIEVzdGV2YW0gW21h
aWx0bzpmZXN0ZXZhbUBnbWFpbC5jb21dDQo+IFNlbnQ6IEZyaWRheSwgT2N0b2JlciAxMCwgMjAx
NCAxMDo1MSBQTQ0KPiBUbzogUmljaGFyZCBaaHUNCj4gQ2M6IGxpbnV4LXBjaUB2Z2VyLmtlcm5l
bC5vcmc7IEd1byBTaGF3bi1SNjUwNzM7IEx1Y2FzIFN0YWNoOyBUaW0gSGFydmV5OyBaaHUNCj4g
UmljaGFyZC1SNjUwMzcNCj4gU3ViamVjdDogUmU6IFtQQVRDSCB2NSA5LzldIEFSTTogaW14NnN4
OiBlbmFibGUgcGNpZSBvbiBpbXg2c3ggc2RiIGJvYXJkDQo+IA0KPiBPbiBGcmksIE9jdCAxMCwg
MjAxNCBhdCAyOjQxIEFNLCBSaWNoYXJkIFpodSA8cmljaGFyZC56aHVAZnJlZXNjYWxlLmNvbT4g
d3JvdGU6DQo+IA0KPiA+ICsgICAgICAgICAgICAgICBwaW5jdHJsX3BjaWU6IHBjaWVncnAgew0K
PiA+ICsgICAgICAgICAgICAgICAgICAgICAgIGZzbCxwaW5zID0gPA0KPiA+ICsgICAgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgTVg2U1hfUEFEX0VORVQxX0NPTF9fR1BJTzJfSU9fMCAweDE3
MDU5DQo+IA0KPiBXaHkgMHgxNzA1OSBpbnN0ZWFkIG9mIHRoZSBkZWZhdWx0IDB4MTBiMD8NCltS
aWNoYXJkXSBJIHJlLXVzZSB0aGUgcGFkIGNmZyB1c2VkIGJ5IHVzZGhjLCBpdCdzIHdvdWxkIGJl
IGxpdHRlciBmYXN0ZXIuDQpBbnl3YXksIGRlZmF1bHQgdmFsdWUgd291bGQgYmUgdXNlZCBsYXRl
ci4NCj4gDQo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgPjsNCj4gPiArICAgICAgICAgICAg
ICAgfTsNCj4gPiArDQo+ID4gKyAgICAgICAgICAgICAgIHBpbmN0cmxfcGNpZV9yZWc6IHBjaWVy
ZWdncnAgew0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAgIGZzbCxwaW5zID0gPA0KPiA+ICsg
ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgTVg2U1hfUEFEX0VORVQxX0NSU19fR1BJTzJf
SU9fMSAweDE3MDU5DQo+IA0KPiBTYW1lIGhlcmUuDQpbUmljaGFyZF0gT2ssIGRlZmF1bHQgdmFs
dWUgd291bGQgYmUgdXNlZCBsYXRlci4NCg0KQmVzdCBSZWdhcmRzDQpSaWNoYXJkIFpodQ0KDQo=