From: Richard Zhu <richard.zhu@freescale.com>
To: <linux-pci@vger.kernel.org>
Cc: <shawn.guo@freescale.com>, <festevam@gmail.com>,
<l.stach@pengutronix.de>, <tharvey@gateworks.com>,
Richard Zhu <r65037@freescale.com>,
Richard Zhu <richard.zhu@freescale.com>
Subject: [PATCH v5 8/9] ARM: imx6sx: add imx6sx pcie related gpr bits definitions
Date: Fri, 10 Oct 2014 13:41:15 +0800 [thread overview]
Message-ID: <1412919676-25344-9-git-send-email-richard.zhu@freescale.com> (raw)
In-Reply-To: <1412919676-25344-1-git-send-email-richard.zhu@freescale.com>
From: Richard Zhu <r65037@freescale.com>
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index ff44374..3273b87 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -301,6 +301,7 @@
#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12)
#define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4)
+#define IMX6Q_GPR12_LOS_LEVEL_9 (0x9 << 4)
#define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
@@ -395,4 +396,12 @@
#define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
#define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)
+/* For imx6sx iomux gpr register field define */
+#define IMX6SX_GPR5_PCIE_BTNRST BIT(19)
+#define IMX6SX_GPR5_PCIE_PERST BIT(18)
+
+#define IMX6SX_GPR12_PCIE_PM_TURN_OFF BIT(16)
+#define IMX6SX_GPR12_PCIE_TEST_PD BIT(30)
+#define IMX6SX_GPR12_RX_EQ_MASK (0x7 << 0)
+#define IMX6SX_GPR12_RX_EQ_2 (0x2 << 0)
#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
--
1.9.1
next prev parent reply other threads:[~2014-10-10 6:11 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-10 5:41 [PATCH v5]PCI: imx6: enable pcie on imx6sx sdb and imx6qdl sabreauto Richard Zhu
2014-10-10 5:41 ` [PATCH v5 1/9] PCI: designware: refine setup_rc and add msi data restore Richard Zhu
2014-10-10 14:42 ` Murali Karicheri
2014-10-20 2:59 ` Hong-Xing.Zhu
2014-10-20 20:00 ` Murali Karicheri
2014-10-12 14:02 ` Lucas Stach
2014-10-10 5:41 ` [PATCH v5 2/9] PCI: designware: fix one potential assignment error of cfg start Richard Zhu
2014-10-10 5:41 ` [PATCH v5 3/9] PCI: imx6: wait the clocks to stabilize after ref_en Richard Zhu
2014-10-10 5:41 ` [PATCH v5 4/9] PCI: imx6: add imx6sx pcie support Richard Zhu
2014-10-10 14:55 ` Fabio Estevam
2014-10-11 8:32 ` Hong-Xing.Zhu
2014-10-12 14:27 ` Lucas Stach
2014-10-13 2:30 ` Hong-Xing.Zhu
2014-10-14 22:12 ` Lucas Stach
2014-10-10 5:41 ` [PATCH v5 5/9] ARM: imx6qdl: enable pcie on imx6qdl sabreauto Richard Zhu
2014-10-10 5:41 ` [PATCH v5 6/9] ARM: imx6: update dts and binding for imx6sx pcie Richard Zhu
2014-10-12 14:35 ` Lucas Stach
2014-10-13 2:32 ` Hong-Xing.Zhu
2014-10-10 5:41 ` [PATCH v5 7/9] ARM: imx6sx: add syscon into gpc dts Richard Zhu
2014-10-10 5:41 ` Richard Zhu [this message]
2014-10-12 14:38 ` [PATCH v5 8/9] ARM: imx6sx: add imx6sx pcie related gpr bits definitions Lucas Stach
2014-10-13 2:34 ` Hong-Xing.Zhu
2014-10-10 5:41 ` [PATCH v5 9/9] ARM: imx6sx: enable pcie on imx6sx sdb board Richard Zhu
2014-10-10 14:50 ` Fabio Estevam
2014-10-11 8:48 ` Hong-Xing.Zhu
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