[PATCH v6]PCI: imx6: enable pcie on imx6sx sdb and imx6qdl sabreauto.

[PATCH v6]PCI: imx6: enable pcie on imx6sx sdb and imx6qdl sabreauto.

[Richard Zhu]

Main changes since the v5:
1.use noirq pm_ops instead of the syscore pm_ops
2.in order to not break compilation, move gpr bits modifications, before
imx6 pcie changes.
3.host init maybe failed, return negative value when there is a failure
in the host init. In responding, the host_init func type had been change from
void to init.

[PATCH v6 01/13] PCI: designware: Refine setup_rc and add msi data
[PATCH v6 02/13] PCI: designware: Set func type of host init to int
[PATCH v6 03/13] PCI: dra7xx: Change the func type of host init
[PATCH v6 04/13] PCI: exynos: Change the func type of host init
[PATCH v6 05/13] PCI: spear: Change the func type of host init
[PATCH v6 06/13] PCI: designware: Fix one potential assignment error
[PATCH v6 07/13] ARM: imx6sx: Add imx6sx pcie related gpr bits
[PATCH v6 08/13] PCI: imx6: Wait the clocks to stabilize after ref_en
[PATCH v6 09/13] PCI: imx6: Add imx6sx pcie support
[PATCH v6 10/13] ARM: imx6qdl: Enable pcie on imx6qdl sabreauto
[PATCH v6 11/13] ARM: imx6: Update dts and binding for imx6sx pcie
[PATCH v6 12/13] ARM: imx6sx: Add syscon into gpc dts
[PATCH v6 13/13] ARM: imx6sx: Enable pcie on imx6sx sdb board

[PATCH v6 01/13] PCI: designware: Refine setup_rc and add msi data restore

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

- move "program correct class for RC" from dw_pcie_host_init()
to dw_pcie_setup_rc(). since this is RC setup, it's
better to contained in dw_pcie_setup_rc function.
Then, RC can be re-setup really by dw_pcie_setup_rc().
- add one store/re-store msi cfg functions. Because that
pcie controller maybe powered off during system suspend,
and the msi data configuration would be lost.
these functions can be used to store/restore the msi data
and msi_enable during the suspend/resume callback.

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 drivers/pci/host/pcie-designware.c | 21 ++++++++++++++++++---
 drivers/pci/host/pcie-designware.h |  3 +++
 2 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 538bbf3..b1f82ff 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -194,6 +194,19 @@ void dw_pcie_msi_init(struct pcie_port *pp)
 	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
 }
 
+void dw_pcie_msi_cfg_store(struct pcie_port *pp)
+{
+	dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, &pp->msi_enable);
+}
+
+void dw_pcie_msi_cfg_restore(struct pcie_port *pp)
+{
+	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
+			virt_to_phys((void *)pp->msi_data));
+	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
+	dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, pp->msi_enable);
+}
+
 static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
 {
 	int flag = 1;
@@ -570,9 +583,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 
 	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
 
-	/* program correct class for RC */
-	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
-
 	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
 	val |= PORT_LOGIC_SPEED_CHANGE;
 	dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
@@ -917,6 +927,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 	val = memlimit | membase;
 	dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
 
+	/* program correct class for RC */
+	dw_pcie_readl_rc(pp, PCI_CLASS_REVISION, &val);
+	val |= PCI_CLASS_BRIDGE_PCI << 16;
+	dw_pcie_writel_rc(pp, val, PCI_CLASS_REVISION);
+
 	/* setup command register */
 	dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
 	val &= 0xffff0000;
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index a476e60..b0bfed0 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -56,6 +56,7 @@ struct pcie_port {
 	int			msi_irq;
 	struct irq_domain	*irq_domain;
 	unsigned long		msi_data;
+	unsigned int		msi_enable;
 	DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
 };
 
@@ -83,6 +84,8 @@ int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
 int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
 void dw_pcie_msi_init(struct pcie_port *pp);
+void dw_pcie_msi_cfg_store(struct pcie_port *pp);
+void dw_pcie_msi_cfg_restore(struct pcie_port *pp);
 int dw_pcie_link_up(struct pcie_port *pp);
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
-- 
1.9.1

Re: [PATCH v6 01/13] PCI: designware: Refine setup_rc and add msi data restore

[Lucas Stach]

Am Donnerstag, den 16.10.2014, 15:52 +0800 schrieb Richard Zhu:
> From: Richard Zhu <r65037@freescale.com>
> 
> - move "program correct class for RC" from dw_pcie_host_init()
> to dw_pcie_setup_rc(). since this is RC setup, it's
> better to contained in dw_pcie_setup_rc function.
> Then, RC can be re-setup really by dw_pcie_setup_rc().
> - add one store/re-store msi cfg functions. Because that
> pcie controller maybe powered off during system suspend,
> and the msi data configuration would be lost.
> these functions can be used to store/restore the msi data
> and msi_enable during the suspend/resume callback.
> 
> Signed-off-by: Richard Zhu <richard.zhu@freescale.com>

NAK for the reasons below.
 
> ---
>  drivers/pci/host/pcie-designware.c | 21 ++++++++++++++++++---
>  drivers/pci/host/pcie-designware.h |  3 +++
>  2 files changed, 21 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 538bbf3..b1f82ff 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -194,6 +194,19 @@ void dw_pcie_msi_init(struct pcie_port *pp)
>  	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
>  }
>  
> +void dw_pcie_msi_cfg_store(struct pcie_port *pp)
> +{
> +	dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, &pp->msi_enable);

You are only saving and restoring this one register. While this might
work for the current implementation that uses only a max of 32 vectors
this is not true in general. At least the imx6 implementation supports
up to 128 vectors, so actually 4 registers might be used here.

> +}
> +
> +void dw_pcie_msi_cfg_restore(struct pcie_port *pp)
> +{
> +	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
> +			virt_to_phys((void *)pp->msi_data));
> +	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
> +	dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, pp->msi_enable);

Murali asked you to take into account the newly added requirements for
older designware cores. You did not.

> +}
> +
>  static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
>  {
>  	int flag = 1;
> @@ -570,9 +583,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>  
>  	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
>  
> -	/* program correct class for RC */
> -	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
> -
>  	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
>  	val |= PORT_LOGIC_SPEED_CHANGE;
>  	dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
> @@ -917,6 +927,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>  	val = memlimit | membase;
>  	dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
>  
> +	/* program correct class for RC */
> +	dw_pcie_readl_rc(pp, PCI_CLASS_REVISION, &val);
> +	val |= PCI_CLASS_BRIDGE_PCI << 16;
> +	dw_pcie_writel_rc(pp, val, PCI_CLASS_REVISION);
> +

This is getting ridiculous. How many time did I ask you to change this
now. This hunk should just read:

+	/* program correct class for RC */
+	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
+

>  	/* setup command register */
>  	dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
>  	val &= 0xffff0000;
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index a476e60..b0bfed0 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -56,6 +56,7 @@ struct pcie_port {
>  	int			msi_irq;
>  	struct irq_domain	*irq_domain;
>  	unsigned long		msi_data;
> +	unsigned int		msi_enable;
>  	DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
>  };
>  
> @@ -83,6 +84,8 @@ int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
>  int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
>  irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
>  void dw_pcie_msi_init(struct pcie_port *pp);
> +void dw_pcie_msi_cfg_store(struct pcie_port *pp);
> +void dw_pcie_msi_cfg_restore(struct pcie_port *pp);
>  int dw_pcie_link_up(struct pcie_port *pp);
>  void dw_pcie_setup_rc(struct pcie_port *pp);
>  int dw_pcie_host_init(struct pcie_port *pp);

RE: [PATCH v6 01/13] PCI: designware: Refine setup_rc and add msi data restore

[Hong-Xing.Zhu]

DQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IEx1Y2FzIFN0YWNoIFttYWls
dG86bC5zdGFjaEBwZW5ndXRyb25peC5kZV0NCj4gU2VudDogVGh1cnNkYXksIE9jdG9iZXIgMTYs
IDIwMTQgNjozNyBQTQ0KPiBUbzogUmljaGFyZCBaaHUNCj4gQ2M6IGxpbnV4LXBjaUB2Z2VyLmtl
cm5lbC5vcmc7IEd1byBTaGF3bi1SNjUwNzM7IGZlc3RldmFtQGdtYWlsLmNvbTsNCj4gdGhhcnZl
eUBnYXRld29ya3MuY29tOyBaaHUgUmljaGFyZC1SNjUwMzcNCj4gU3ViamVjdDogUmU6IFtQQVRD
SCB2NiAwMS8xM10gUENJOiBkZXNpZ253YXJlOiBSZWZpbmUgc2V0dXBfcmMgYW5kIGFkZCBtc2kN
Cj4gZGF0YSByZXN0b3JlDQo+IA0KPiBBbSBEb25uZXJzdGFnLCBkZW4gMTYuMTAuMjAxNCwgMTU6
NTIgKzA4MDAgc2NocmllYiBSaWNoYXJkIFpodToNCj4gPiBGcm9tOiBSaWNoYXJkIFpodSA8cjY1
MDM3QGZyZWVzY2FsZS5jb20+DQo+ID4NCj4gPiAtIG1vdmUgInByb2dyYW0gY29ycmVjdCBjbGFz
cyBmb3IgUkMiIGZyb20gZHdfcGNpZV9ob3N0X2luaXQoKSB0bw0KPiA+IGR3X3BjaWVfc2V0dXBf
cmMoKS4gc2luY2UgdGhpcyBpcyBSQyBzZXR1cCwgaXQncyBiZXR0ZXIgdG8gY29udGFpbmVkDQo+
ID4gaW4gZHdfcGNpZV9zZXR1cF9yYyBmdW5jdGlvbi4NCj4gPiBUaGVuLCBSQyBjYW4gYmUgcmUt
c2V0dXAgcmVhbGx5IGJ5IGR3X3BjaWVfc2V0dXBfcmMoKS4NCj4gPiAtIGFkZCBvbmUgc3RvcmUv
cmUtc3RvcmUgbXNpIGNmZyBmdW5jdGlvbnMuIEJlY2F1c2UgdGhhdCBwY2llDQo+ID4gY29udHJv
bGxlciBtYXliZSBwb3dlcmVkIG9mZiBkdXJpbmcgc3lzdGVtIHN1c3BlbmQsIGFuZCB0aGUgbXNp
IGRhdGENCj4gPiBjb25maWd1cmF0aW9uIHdvdWxkIGJlIGxvc3QuDQo+ID4gdGhlc2UgZnVuY3Rp
b25zIGNhbiBiZSB1c2VkIHRvIHN0b3JlL3Jlc3RvcmUgdGhlIG1zaSBkYXRhIGFuZA0KPiA+IG1z
aV9lbmFibGUgZHVyaW5nIHRoZSBzdXNwZW5kL3Jlc3VtZSBjYWxsYmFjay4NCj4gPg0KPiA+IFNp
Z25lZC1vZmYtYnk6IFJpY2hhcmQgWmh1IDxyaWNoYXJkLnpodUBmcmVlc2NhbGUuY29tPg0KPiAN
Cj4gTkFLIGZvciB0aGUgcmVhc29ucyBiZWxvdy4NCj4gDQo+ID4gLS0tDQo+ID4gIGRyaXZlcnMv
cGNpL2hvc3QvcGNpZS1kZXNpZ253YXJlLmMgfCAyMSArKysrKysrKysrKysrKysrKystLS0NCj4g
PiBkcml2ZXJzL3BjaS9ob3N0L3BjaWUtZGVzaWdud2FyZS5oIHwgIDMgKysrDQo+ID4gIDIgZmls
ZXMgY2hhbmdlZCwgMjEgaW5zZXJ0aW9ucygrKSwgMyBkZWxldGlvbnMoLSkNCj4gPg0KPiA+IGRp
ZmYgLS1naXQgYS9kcml2ZXJzL3BjaS9ob3N0L3BjaWUtZGVzaWdud2FyZS5jDQo+ID4gYi9kcml2
ZXJzL3BjaS9ob3N0L3BjaWUtZGVzaWdud2FyZS5jDQo+ID4gaW5kZXggNTM4YmJmMy4uYjFmODJm
ZiAxMDA2NDQNCj4gPiAtLS0gYS9kcml2ZXJzL3BjaS9ob3N0L3BjaWUtZGVzaWdud2FyZS5jDQo+
ID4gKysrIGIvZHJpdmVycy9wY2kvaG9zdC9wY2llLWRlc2lnbndhcmUuYw0KPiA+IEBAIC0xOTQs
NiArMTk0LDE5IEBAIHZvaWQgZHdfcGNpZV9tc2lfaW5pdChzdHJ1Y3QgcGNpZV9wb3J0ICpwcCkN
Cj4gPiAgCWR3X3BjaWVfd3Jfb3duX2NvbmYocHAsIFBDSUVfTVNJX0FERFJfSEksIDQsIDApOyAg
fQ0KPiA+DQo+ID4gK3ZvaWQgZHdfcGNpZV9tc2lfY2ZnX3N0b3JlKHN0cnVjdCBwY2llX3BvcnQg
KnBwKSB7DQo+ID4gKwlkd19wY2llX3JkX293bl9jb25mKHBwLCBQQ0lFX01TSV9JTlRSMF9FTkFC
TEUsIDQsICZwcC0+bXNpX2VuYWJsZSk7DQo+IA0KPiBZb3UgYXJlIG9ubHkgc2F2aW5nIGFuZCBy
ZXN0b3JpbmcgdGhpcyBvbmUgcmVnaXN0ZXIuIFdoaWxlIHRoaXMgbWlnaHQgd29yayBmb3INCj4g
dGhlIGN1cnJlbnQgaW1wbGVtZW50YXRpb24gdGhhdCB1c2VzIG9ubHkgYSBtYXggb2YgMzIgdmVj
dG9ycyB0aGlzIGlzIG5vdCB0cnVlDQo+IGluIGdlbmVyYWwuIEF0IGxlYXN0IHRoZSBpbXg2IGlt
cGxlbWVudGF0aW9uIHN1cHBvcnRzIHVwIHRvIDEyOCB2ZWN0b3JzLCBzbw0KPiBhY3R1YWxseSA0
IHJlZ2lzdGVycyBtaWdodCBiZSB1c2VkIGhlcmUuDQo+DQpbUmljaGFyZF0gT2ssIGFsbCB0aGUg
Zm91ciByZWdpc3RlcnMgd291bGQgYmUgc3RvcmVkL3JlLXN0b3JlZC4NCiANCj4gPiArfQ0KPiA+
ICsNCj4gPiArdm9pZCBkd19wY2llX21zaV9jZmdfcmVzdG9yZShzdHJ1Y3QgcGNpZV9wb3J0ICpw
cCkgew0KPiA+ICsJZHdfcGNpZV93cl9vd25fY29uZihwcCwgUENJRV9NU0lfQUREUl9MTywgNCwN
Cj4gPiArCQkJdmlydF90b19waHlzKCh2b2lkICopcHAtPm1zaV9kYXRhKSk7DQo+ID4gKwlkd19w
Y2llX3dyX293bl9jb25mKHBwLCBQQ0lFX01TSV9BRERSX0hJLCA0LCAwKTsNCj4gPiArCWR3X3Bj
aWVfd3Jfb3duX2NvbmYocHAsIFBDSUVfTVNJX0lOVFIwX0VOQUJMRSwgNCwgcHAtPm1zaV9lbmFi
bGUpOw0KPiANCj4gTXVyYWxpIGFza2VkIHlvdSB0byB0YWtlIGludG8gYWNjb3VudCB0aGUgbmV3
bHkgYWRkZWQgcmVxdWlyZW1lbnRzIGZvciBvbGRlcg0KPiBkZXNpZ253YXJlIGNvcmVzLiBZb3Ug
ZGlkIG5vdC4NCltSaWNoYXJkXSBTb3JyeSwgTXVyYWxpJ3MgY29tbWVudHMgaXMgbWlzc2VkIGJl
Zm9yZSwgd291bGQgYmUgYWRkZWQgbGF0ZXIuDQo+IA0KPiA+ICt9DQo+ID4gKw0KPiA+ICBzdGF0
aWMgaW50IGZpbmRfdmFsaWRfcG9zMChzdHJ1Y3QgcGNpZV9wb3J0ICpwcCwgaW50IG1zZ3ZlYywg
aW50IHBvcywNCj4gPiBpbnQgKnBvczApICB7DQo+ID4gIAlpbnQgZmxhZyA9IDE7DQo+ID4gQEAg
LTU3MCw5ICs1ODMsNiBAQCBpbnQgX19pbml0IGR3X3BjaWVfaG9zdF9pbml0KHN0cnVjdCBwY2ll
X3BvcnQgKnBwKQ0KPiA+DQo+ID4gIAlkd19wY2llX3dyX293bl9jb25mKHBwLCBQQ0lfQkFTRV9B
RERSRVNTXzAsIDQsIDApOw0KPiA+DQo+ID4gLQkvKiBwcm9ncmFtIGNvcnJlY3QgY2xhc3MgZm9y
IFJDICovDQo+ID4gLQlkd19wY2llX3dyX293bl9jb25mKHBwLCBQQ0lfQ0xBU1NfREVWSUNFLCAy
LCBQQ0lfQ0xBU1NfQlJJREdFX1BDSSk7DQo+ID4gLQ0KPiA+ICAJZHdfcGNpZV9yZF9vd25fY29u
ZihwcCwgUENJRV9MSU5LX1dJRFRIX1NQRUVEX0NPTlRST0wsIDQsICZ2YWwpOw0KPiA+ICAJdmFs
IHw9IFBPUlRfTE9HSUNfU1BFRURfQ0hBTkdFOw0KPiA+ICAJZHdfcGNpZV93cl9vd25fY29uZihw
cCwgUENJRV9MSU5LX1dJRFRIX1NQRUVEX0NPTlRST0wsIDQsIHZhbCk7IEBADQo+ID4gLTkxNyw2
ICs5MjcsMTEgQEAgdm9pZCBkd19wY2llX3NldHVwX3JjKHN0cnVjdCBwY2llX3BvcnQgKnBwKQ0K
PiA+ICAJdmFsID0gbWVtbGltaXQgfCBtZW1iYXNlOw0KPiA+ICAJZHdfcGNpZV93cml0ZWxfcmMo
cHAsIHZhbCwgUENJX01FTU9SWV9CQVNFKTsNCj4gPg0KPiA+ICsJLyogcHJvZ3JhbSBjb3JyZWN0
IGNsYXNzIGZvciBSQyAqLw0KPiA+ICsJZHdfcGNpZV9yZWFkbF9yYyhwcCwgUENJX0NMQVNTX1JF
VklTSU9OLCAmdmFsKTsNCj4gPiArCXZhbCB8PSBQQ0lfQ0xBU1NfQlJJREdFX1BDSSA8PCAxNjsN
Cj4gPiArCWR3X3BjaWVfd3JpdGVsX3JjKHBwLCB2YWwsIFBDSV9DTEFTU19SRVZJU0lPTik7DQo+
ID4gKw0KPiANCj4gVGhpcyBpcyBnZXR0aW5nIHJpZGljdWxvdXMuIEhvdyBtYW55IHRpbWUgZGlk
IEkgYXNrIHlvdSB0byBjaGFuZ2UgdGhpcyBub3cuDQo+IFRoaXMgaHVuayBzaG91bGQganVzdCBy
ZWFkOg0KPiANCj4gKwkvKiBwcm9ncmFtIGNvcnJlY3QgY2xhc3MgZm9yIFJDICovDQo+ICsJZHdf
cGNpZV93cl9vd25fY29uZihwcCwgUENJX0NMQVNTX0RFVklDRSwgMiwgUENJX0NMQVNTX0JSSURH
RV9QQ0kpOw0KPiArDQo+IA0KW1JpY2hhcmRdIE9rLCB3b3VsZCBiZSBrZXB0IHRoaXMgd2F5LiBU
aGFua3MuDQoNCj4gPiAgCS8qIHNldHVwIGNvbW1hbmQgcmVnaXN0ZXIgKi8NCj4gPiAgCWR3X3Bj
aWVfcmVhZGxfcmMocHAsIFBDSV9DT01NQU5ELCAmdmFsKTsNCj4gPiAgCXZhbCAmPSAweGZmZmYw
MDAwOw0KPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3BjaS9ob3N0L3BjaWUtZGVzaWdud2FyZS5o
DQo+ID4gYi9kcml2ZXJzL3BjaS9ob3N0L3BjaWUtZGVzaWdud2FyZS5oDQo+ID4gaW5kZXggYTQ3
NmU2MC4uYjBiZmVkMCAxMDA2NDQNCj4gPiAtLS0gYS9kcml2ZXJzL3BjaS9ob3N0L3BjaWUtZGVz
aWdud2FyZS5oDQo+ID4gKysrIGIvZHJpdmVycy9wY2kvaG9zdC9wY2llLWRlc2lnbndhcmUuaA0K
PiA+IEBAIC01Niw2ICs1Niw3IEBAIHN0cnVjdCBwY2llX3BvcnQgew0KPiA+ICAJaW50CQkJbXNp
X2lycTsNCj4gPiAgCXN0cnVjdCBpcnFfZG9tYWluCSppcnFfZG9tYWluOw0KPiA+ICAJdW5zaWdu
ZWQgbG9uZwkJbXNpX2RhdGE7DQo+ID4gKwl1bnNpZ25lZCBpbnQJCW1zaV9lbmFibGU7DQo+ID4g
IAlERUNMQVJFX0JJVE1BUChtc2lfaXJxX2luX3VzZSwgTUFYX01TSV9JUlFTKTsgIH07DQo+ID4N
Cj4gPiBAQCAtODMsNiArODQsOCBAQCBpbnQgZHdfcGNpZV9jZmdfcmVhZCh2b2lkIF9faW9tZW0g
KmFkZHIsIGludCB3aGVyZSwNCj4gPiBpbnQgc2l6ZSwgdTMyICp2YWwpOyAgaW50IGR3X3BjaWVf
Y2ZnX3dyaXRlKHZvaWQgX19pb21lbSAqYWRkciwgaW50DQo+ID4gd2hlcmUsIGludCBzaXplLCB1
MzIgdmFsKTsgIGlycXJldHVybl90IGR3X2hhbmRsZV9tc2lfaXJxKHN0cnVjdA0KPiA+IHBjaWVf
cG9ydCAqcHApOyAgdm9pZCBkd19wY2llX21zaV9pbml0KHN0cnVjdCBwY2llX3BvcnQgKnBwKTsN
Cj4gPiArdm9pZCBkd19wY2llX21zaV9jZmdfc3RvcmUoc3RydWN0IHBjaWVfcG9ydCAqcHApOyB2
b2lkDQo+ID4gK2R3X3BjaWVfbXNpX2NmZ19yZXN0b3JlKHN0cnVjdCBwY2llX3BvcnQgKnBwKTsN
Cj4gPiAgaW50IGR3X3BjaWVfbGlua191cChzdHJ1Y3QgcGNpZV9wb3J0ICpwcCk7ICB2b2lkDQo+
ID4gZHdfcGNpZV9zZXR1cF9yYyhzdHJ1Y3QgcGNpZV9wb3J0ICpwcCk7ICBpbnQgZHdfcGNpZV9o
b3N0X2luaXQoc3RydWN0DQo+ID4gcGNpZV9wb3J0ICpwcCk7DQo+IA0KDQoNCkJlc3QgUmVnYXJk
cw0KUmljaGFyZCBaaHUNCg0K

[PATCH v6 02/13] PCI: designware: Set func type of host init to int

[Richard Zhu]

host init maybe failed, change the func type of host_init
defined in struct pci_host_ops from void to int.

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 drivers/pci/host/pcie-designware.c | 7 +++++--
 drivers/pci/host/pcie-designware.h | 2 +-
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index b1f82ff..1a2b477 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -578,8 +578,11 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 		}
 	}
 
-	if (pp->ops->host_init)
-		pp->ops->host_init(pp);
+	if (pp->ops->host_init) {
+		ret = pp->ops->host_init(pp);
+		if (ret < 0)
+			return ret;
+	}
 
 	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
 
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index b0bfed0..57ab11d 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -72,7 +72,7 @@ struct pcie_host_ops {
 	int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
 			unsigned int devfn, int where, int size, u32 val);
 	int (*link_up)(struct pcie_port *pp);
-	void (*host_init)(struct pcie_port *pp);
+	int (*host_init)(struct pcie_port *pp);
 	void (*msi_set_irq)(struct pcie_port *pp, int irq);
 	void (*msi_clear_irq)(struct pcie_port *pp, int irq);
 	u32 (*get_msi_data)(struct pcie_port *pp);
-- 
1.9.1

Re: [PATCH v6 02/13] PCI: designware: Set func type of host init to int

[Lucas Stach]

Am Donnerstag, den 16.10.2014, 15:52 +0800 schrieb Richard Zhu:
> host init maybe failed, change the func type of host_init
> defined in struct pci_host_ops from void to int.
> 
> Signed-off-by: Richard Zhu <richard.zhu@freescale.com>

NAK. You are breaking compilation within the series here. If you are
going to change the prototype the dependant changes need to be in the
same patch. So squash in at least patch 3-5 plus the imx6 change.

> ---
>  drivers/pci/host/pcie-designware.c | 7 +++++--
>  drivers/pci/host/pcie-designware.h | 2 +-
>  2 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index b1f82ff..1a2b477 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -578,8 +578,11 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>  		}
>  	}
>  
> -	if (pp->ops->host_init)
> -		pp->ops->host_init(pp);
> +	if (pp->ops->host_init) {
> +		ret = pp->ops->host_init(pp);
> +		if (ret < 0)
> +			return ret;
> +	}
>  
>  	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
>  
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index b0bfed0..57ab11d 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -72,7 +72,7 @@ struct pcie_host_ops {
>  	int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
>  			unsigned int devfn, int where, int size, u32 val);
>  	int (*link_up)(struct pcie_port *pp);
> -	void (*host_init)(struct pcie_port *pp);
> +	int (*host_init)(struct pcie_port *pp);
>  	void (*msi_set_irq)(struct pcie_port *pp, int irq);
>  	void (*msi_clear_irq)(struct pcie_port *pp, int irq);
>  	u32 (*get_msi_data)(struct pcie_port *pp);

RE: [PATCH v6 02/13] PCI: designware: Set func type of host init to int

[Hong-Xing.Zhu]

DQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IEx1Y2FzIFN0YWNoIFttYWls
dG86bC5zdGFjaEBwZW5ndXRyb25peC5kZV0NCj4gU2VudDogVGh1cnNkYXksIE9jdG9iZXIgMTYs
IDIwMTQgNjozOSBQTQ0KPiBUbzogUmljaGFyZCBaaHUNCj4gQ2M6IGxpbnV4LXBjaUB2Z2VyLmtl
cm5lbC5vcmc7IEd1byBTaGF3bi1SNjUwNzM7IGZlc3RldmFtQGdtYWlsLmNvbTsNCj4gdGhhcnZl
eUBnYXRld29ya3MuY29tDQo+IFN1YmplY3Q6IFJlOiBbUEFUQ0ggdjYgMDIvMTNdIFBDSTogZGVz
aWdud2FyZTogU2V0IGZ1bmMgdHlwZSBvZiBob3N0IGluaXQgdG8NCj4gaW50DQo+IA0KPiBBbSBE
b25uZXJzdGFnLCBkZW4gMTYuMTAuMjAxNCwgMTU6NTIgKzA4MDAgc2NocmllYiBSaWNoYXJkIFpo
dToNCj4gPiBob3N0IGluaXQgbWF5YmUgZmFpbGVkLCBjaGFuZ2UgdGhlIGZ1bmMgdHlwZSBvZiBo
b3N0X2luaXQgZGVmaW5lZCBpbg0KPiA+IHN0cnVjdCBwY2lfaG9zdF9vcHMgZnJvbSB2b2lkIHRv
IGludC4NCj4gPg0KPiA+IFNpZ25lZC1vZmYtYnk6IFJpY2hhcmQgWmh1IDxyaWNoYXJkLnpodUBm
cmVlc2NhbGUuY29tPg0KPiANCj4gTkFLLiBZb3UgYXJlIGJyZWFraW5nIGNvbXBpbGF0aW9uIHdp
dGhpbiB0aGUgc2VyaWVzIGhlcmUuIElmIHlvdSBhcmUgZ29pbmcgdG8NCj4gY2hhbmdlIHRoZSBw
cm90b3R5cGUgdGhlIGRlcGVuZGFudCBjaGFuZ2VzIG5lZWQgdG8gYmUgaW4gdGhlIHNhbWUgcGF0
Y2guIFNvDQo+IHNxdWFzaCBpbiBhdCBsZWFzdCBwYXRjaCAzLTUgcGx1cyB0aGUgaW14NiBjaGFu
Z2UuDQpbUmljaGFyZF0gU28sIHRoaXMgcGF0Y2ggc2hvdWxkIGJlIHNxdWFzaGVkIHdpdGggcGF0
Y2gzLTUsIGFuZCB0aGUgIlBDSTogaW14NjogQWRkIGlteDZzeCBwY2llIHN1cHBvcnQiLg0KVGhh
bmtzLg0KDQo+IA0KPiA+IC0tLQ0KPiA+ICBkcml2ZXJzL3BjaS9ob3N0L3BjaWUtZGVzaWdud2Fy
ZS5jIHwgNyArKysrKy0tDQo+ID4gZHJpdmVycy9wY2kvaG9zdC9wY2llLWRlc2lnbndhcmUuaCB8
IDIgKy0NCj4gPiAgMiBmaWxlcyBjaGFuZ2VkLCA2IGluc2VydGlvbnMoKyksIDMgZGVsZXRpb25z
KC0pDQo+ID4NCj4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9wY2kvaG9zdC9wY2llLWRlc2lnbndh
cmUuYw0KPiA+IGIvZHJpdmVycy9wY2kvaG9zdC9wY2llLWRlc2lnbndhcmUuYw0KPiA+IGluZGV4
IGIxZjgyZmYuLjFhMmI0NzcgMTAwNjQ0DQo+ID4gLS0tIGEvZHJpdmVycy9wY2kvaG9zdC9wY2ll
LWRlc2lnbndhcmUuYw0KPiA+ICsrKyBiL2RyaXZlcnMvcGNpL2hvc3QvcGNpZS1kZXNpZ253YXJl
LmMNCj4gPiBAQCAtNTc4LDggKzU3OCwxMSBAQCBpbnQgX19pbml0IGR3X3BjaWVfaG9zdF9pbml0
KHN0cnVjdCBwY2llX3BvcnQgKnBwKQ0KPiA+ICAJCX0NCj4gPiAgCX0NCj4gPg0KPiA+IC0JaWYg
KHBwLT5vcHMtPmhvc3RfaW5pdCkNCj4gPiAtCQlwcC0+b3BzLT5ob3N0X2luaXQocHApOw0KPiA+
ICsJaWYgKHBwLT5vcHMtPmhvc3RfaW5pdCkgew0KPiA+ICsJCXJldCA9IHBwLT5vcHMtPmhvc3Rf
aW5pdChwcCk7DQo+ID4gKwkJaWYgKHJldCA8IDApDQo+ID4gKwkJCXJldHVybiByZXQ7DQo+ID4g
Kwl9DQo+ID4NCj4gPiAgCWR3X3BjaWVfd3Jfb3duX2NvbmYocHAsIFBDSV9CQVNFX0FERFJFU1Nf
MCwgNCwgMCk7DQo+ID4NCj4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9wY2kvaG9zdC9wY2llLWRl
c2lnbndhcmUuaA0KPiA+IGIvZHJpdmVycy9wY2kvaG9zdC9wY2llLWRlc2lnbndhcmUuaA0KPiA+
IGluZGV4IGIwYmZlZDAuLjU3YWIxMWQgMTAwNjQ0DQo+ID4gLS0tIGEvZHJpdmVycy9wY2kvaG9z
dC9wY2llLWRlc2lnbndhcmUuaA0KPiA+ICsrKyBiL2RyaXZlcnMvcGNpL2hvc3QvcGNpZS1kZXNp
Z253YXJlLmgNCj4gPiBAQCAtNzIsNyArNzIsNyBAQCBzdHJ1Y3QgcGNpZV9ob3N0X29wcyB7DQo+
ID4gIAlpbnQgKCp3cl9vdGhlcl9jb25mKShzdHJ1Y3QgcGNpZV9wb3J0ICpwcCwgc3RydWN0IHBj
aV9idXMgKmJ1cywNCj4gPiAgCQkJdW5zaWduZWQgaW50IGRldmZuLCBpbnQgd2hlcmUsIGludCBz
aXplLCB1MzIgdmFsKTsNCj4gPiAgCWludCAoKmxpbmtfdXApKHN0cnVjdCBwY2llX3BvcnQgKnBw
KTsNCj4gPiAtCXZvaWQgKCpob3N0X2luaXQpKHN0cnVjdCBwY2llX3BvcnQgKnBwKTsNCj4gPiAr
CWludCAoKmhvc3RfaW5pdCkoc3RydWN0IHBjaWVfcG9ydCAqcHApOw0KPiA+ICAJdm9pZCAoKm1z
aV9zZXRfaXJxKShzdHJ1Y3QgcGNpZV9wb3J0ICpwcCwgaW50IGlycSk7DQo+ID4gIAl2b2lkICgq
bXNpX2NsZWFyX2lycSkoc3RydWN0IHBjaWVfcG9ydCAqcHAsIGludCBpcnEpOw0KPiA+ICAJdTMy
ICgqZ2V0X21zaV9kYXRhKShzdHJ1Y3QgcGNpZV9wb3J0ICpwcCk7DQo+IA0KDQoNCkJlc3QgUmVn
YXJkcw0KUmljaGFyZCBaaHUNCg0K

[PATCH v6 03/13] PCI: dra7xx: Change the func type of host init

[Richard Zhu]

In order to avoid compilation warning, change
the func type of host init from void to int.

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 drivers/pci/host/pci-dra7xx.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index 52b34fe..7b11968 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -141,13 +141,15 @@ static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)
 				   LEG_EP_INTERRUPTS);
 }
 
-static void dra7xx_pcie_host_init(struct pcie_port *pp)
+static int dra7xx_pcie_host_init(struct pcie_port *pp)
 {
 	dw_pcie_setup_rc(pp);
 	dra7xx_pcie_establish_link(pp);
 	if (IS_ENABLED(CONFIG_PCI_MSI))
 		dw_pcie_msi_init(pp);
 	dra7xx_pcie_enable_interrupts(pp);
+
+	return 0;
 }
 
 static struct pcie_host_ops dra7xx_pcie_host_ops = {
-- 
1.9.1

[PATCH v6 04/13] PCI: exynos: Change the func type of host init

[Richard Zhu]

In order to avoid compilation warning, change
the func type of host init from void to int.

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 drivers/pci/host/pci-exynos.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index c5d0ca3..606d0a9 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -494,10 +494,12 @@ static int exynos_pcie_link_up(struct pcie_port *pp)
 	return 0;
 }
 
-static void exynos_pcie_host_init(struct pcie_port *pp)
+static int exynos_pcie_host_init(struct pcie_port *pp)
 {
 	exynos_pcie_establish_link(pp);
 	exynos_pcie_enable_interrupts(pp);
+
+	return 0;
 }
 
 static struct pcie_host_ops exynos_pcie_host_ops = {
-- 
1.9.1

[PATCH v6 05/13] PCI: spear: Change the func type of host init

[Richard Zhu]

In order to avoid compilation warning, change
the func type of host init from void to int.

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 drivers/pci/host/pcie-spear13xx.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c
index 6dea9e4..b8fd76b 100644
--- a/drivers/pci/host/pcie-spear13xx.c
+++ b/drivers/pci/host/pcie-spear13xx.c
@@ -258,10 +258,12 @@ static int spear13xx_pcie_link_up(struct pcie_port *pp)
 	return 0;
 }
 
-static void spear13xx_pcie_host_init(struct pcie_port *pp)
+static int spear13xx_pcie_host_init(struct pcie_port *pp)
 {
 	spear13xx_pcie_establish_link(pp);
 	spear13xx_pcie_enable_interrupts(pp);
+
+	return 0;
 }
 
 static struct pcie_host_ops spear13xx_pcie_host_ops = {
-- 
1.9.1

[PATCH v6 06/13] PCI: designware: Fix one potential assignment error of cfg start

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

if va_cfg0_base/va_cfg1_base are initialized by
designware core, the pp->cfg.start is not initialized
properly, when IORESOURCE_MEM "config" is represented
as cfg space resource.
solution: assign cfg_res->start to pp->cfg.start.

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 drivers/pci/host/pcie-designware.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 1a2b477..3edd94d 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -450,6 +450,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 	if (cfg_res) {
 		pp->config.cfg0_size = resource_size(cfg_res)/2;
 		pp->config.cfg1_size = resource_size(cfg_res)/2;
+		pp->cfg.start = cfg_res->start;
 		pp->cfg0_base = cfg_res->start;
 		pp->cfg1_base = cfg_res->start + pp->config.cfg0_size;
 
-- 
1.9.1

[PATCH v6 07/13] ARM: imx6sx: Add imx6sx pcie related gpr bits definitions

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index ff44374..3273b87 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -301,6 +301,7 @@
 #define IMX6Q_GPR12_DEVICE_TYPE			(0xf << 12)
 #define IMX6Q_GPR12_PCIE_CTL_2			BIT(10)
 #define IMX6Q_GPR12_LOS_LEVEL			(0x1f << 4)
+#define IMX6Q_GPR12_LOS_LEVEL_9			(0x9 << 4)
 
 #define IMX6Q_GPR13_SDMA_STOP_REQ		BIT(30)
 #define IMX6Q_GPR13_CAN2_STOP_REQ		BIT(29)
@@ -395,4 +396,12 @@
 #define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK    (0x3 << 17)
 #define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK    (0x1 << 14)
 
+/* For imx6sx iomux gpr register field define */
+#define IMX6SX_GPR5_PCIE_BTNRST			BIT(19)
+#define IMX6SX_GPR5_PCIE_PERST			BIT(18)
+
+#define IMX6SX_GPR12_PCIE_PM_TURN_OFF		BIT(16)
+#define IMX6SX_GPR12_PCIE_TEST_PD		BIT(30)
+#define IMX6SX_GPR12_RX_EQ_MASK			(0x7 << 0)
+#define IMX6SX_GPR12_RX_EQ_2			(0x2 << 0)
 #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
-- 
1.9.1

[PATCH v6 08/13] PCI: imx6: Wait the clocks to stabilize after ref_en

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

For boards without a reset gpio we skip the delay between enabling
the pcie_ref_clk and touching the RC registers for configuration.
System would be hangs when the clocks are not yet settled in the DW
PCIe core. So we need to make sure that there is always an
appropriate delay between those two actions.

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
---
 drivers/pci/host/pci-imx6.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index 233fe8a..eac96fb 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -275,15 +275,22 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 		goto err_pcie;
 	}
 
-	/* allow the clocks to stabilize */
-	usleep_range(200, 500);
-
 	/* power up core phy and enable ref clock */
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
+	/*
+	 * the async reset input need ref clock to sync internally,
+	 * when the ref clock comes after reset, internal synced
+	 * reset time is too short , cannot meet the requirement.
+	 * add one ~10us delay here.
+	 */
+	udelay(10);
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
 
+	/* allow the clocks to stabilize */
+	usleep_range(200, 500);
+
 	/* Some boards don't have PCIe reset GPIO. */
 	if (gpio_is_valid(imx6_pcie->reset_gpio)) {
 		gpio_set_value(imx6_pcie->reset_gpio, 0);
-- 
1.9.1

[PATCH v6 09/13] PCI: imx6: Add imx6sx pcie support

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

- imx6sx pcie has its own standalone pcie power supply.
In order to turn on the imx6sx pcie power during
initialization. Add the pcie regulator and the gpc regmap
into the imx6sx pcie structure.
- imx6sx pcie has the new added reset mechanism, add the
reset operations into the initialization.
- register one PM call-back, enter/exit L2 state during
system suspend/resume.
use noirq pm_ops instead of the general pm_ops in dev_pm_ops,
since cfg read/write may occurs after suspend and before resume.
do msi store/re-store in suspend/resume callbacks, since
controller maybe turned off, and these msi cfg maybe lost
in suspend.
- disp_axi clock is required by pcie inbound axi port actually.
Add one more clock named pcie_inbound_axi for imx6sx pcie.
- host init maybe failed, return negative value when
there is a failure in the host init.

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 drivers/pci/host/pci-imx6.c | 204 +++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 183 insertions(+), 21 deletions(-)

diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index eac96fb..dfe2334 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -22,6 +22,7 @@
 #include <linux/pci.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
 #include <linux/resource.h>
 #include <linux/signal.h>
 #include <linux/types.h>
@@ -35,9 +36,12 @@ struct imx6_pcie {
 	int			reset_gpio;
 	struct clk		*pcie_bus;
 	struct clk		*pcie_phy;
+	struct clk		*pcie_inbound_axi;
 	struct clk		*pcie;
 	struct pcie_port	pp;
 	struct regmap		*iomuxc_gpr;
+	struct regmap		*gpc_ips_reg;
+	struct regulator	*pcie_phy_regulator;
 	void __iomem		*mem_base;
 };
 
@@ -77,6 +81,18 @@ struct imx6_pcie {
 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
 
+/* GPC PCIE PHY bit definitions */
+#define GPC_CNTR			0
+#define GPC_CNTR_PCIE_PHY_PUP_REQ	BIT(7)
+
+static inline bool is_imx6sx_pcie(struct imx6_pcie *imx6_pcie)
+{
+	struct pcie_port *pp = &imx6_pcie->pp;
+	struct device_node *np = pp->dev->of_node;
+
+	return of_device_is_compatible(np, "fsl,imx6sx-pcie");
+}
+
 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
 {
 	u32 val;
@@ -275,18 +291,30 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 		goto err_pcie;
 	}
 
-	/* power up core phy and enable ref clock */
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
-	/*
-	 * the async reset input need ref clock to sync internally,
-	 * when the ref clock comes after reset, internal synced
-	 * reset time is too short , cannot meet the requirement.
-	 * add one ~10us delay here.
-	 */
-	udelay(10);
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
+	if (is_imx6sx_pcie(imx6_pcie)) {
+		ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
+		if (ret) {
+			dev_err(pp->dev, "unable to enable pcie clock\n");
+			goto err_inbound_axi;
+		}
+
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				IMX6SX_GPR12_PCIE_TEST_PD, 0);
+	} else {
+		/* power up core phy and enable ref clock */
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+				IMX6Q_GPR1_PCIE_TEST_PD, 0);
+		/*
+		 * the async reset input need ref clock to sync internally,
+		 * when the ref clock comes after reset, internal synced
+		 * reset time is too short , cannot meet the requirement.
+		 * add one ~10us delay here.
+		 */
+		udelay(10);
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+				IMX6Q_GPR1_PCIE_REF_CLK_EN,
+				IMX6Q_GPR1_PCIE_REF_CLK_EN);
+	}
 
 	/* allow the clocks to stabilize */
 	usleep_range(200, 500);
@@ -297,8 +325,19 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 		msleep(100);
 		gpio_set_value(imx6_pcie->reset_gpio, 1);
 	}
+
+	/*
+	 * Release the PCIe PHY reset here, that we have set in
+	 * imx6_pcie_init_phy() now
+	 */
+	if (is_imx6sx_pcie(imx6_pcie))
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+				IMX6SX_GPR5_PCIE_BTNRST, 0);
+
 	return 0;
 
+err_inbound_axi:
+	clk_disable_unprepare(imx6_pcie->pcie);
 err_pcie:
 	clk_disable_unprepare(imx6_pcie->pcie_bus);
 err_pcie_bus:
@@ -308,9 +347,31 @@ err_pcie_phy:
 
 }
 
-static void imx6_pcie_init_phy(struct pcie_port *pp)
+static int imx6_pcie_init_phy(struct pcie_port *pp)
 {
 	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
+	int ret;
+
+	/* Power up the separate domain available on i.MX6SX */
+	if (is_imx6sx_pcie(imx6_pcie)) {
+		/* Force PCIe PHY reset */
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+				IMX6SX_GPR5_PCIE_BTNRST,
+				IMX6SX_GPR5_PCIE_BTNRST);
+
+		regmap_update_bits(imx6_pcie->gpc_ips_reg, GPC_CNTR,
+				GPC_CNTR_PCIE_PHY_PUP_REQ,
+				GPC_CNTR_PCIE_PHY_PUP_REQ);
+		regulator_set_voltage(imx6_pcie->pcie_phy_regulator,
+				1100000, 1100000);
+		ret = regulator_enable(imx6_pcie->pcie_phy_regulator);
+		if (ret) {
+			dev_err(pp->dev, "failed to enable pcie regulator.\n");
+			return ret;
+		}
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				IMX6SX_GPR12_RX_EQ_MASK, IMX6SX_GPR12_RX_EQ_2);
+	}
 
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 			IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
@@ -319,7 +380,7 @@ static void imx6_pcie_init_phy(struct pcie_port *pp)
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 			IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
-			IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
+			IMX6Q_GPR12_LOS_LEVEL, IMX6Q_GPR12_LOS_LEVEL_9);
 
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 			IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
@@ -331,6 +392,8 @@ static void imx6_pcie_init_phy(struct pcie_port *pp)
 			IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 			IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
+
+	return 0;
 }
 
 static int imx6_pcie_wait_for_link(struct pcie_port *pp)
@@ -377,7 +440,8 @@ static int imx6_pcie_start_link(struct pcie_port *pp)
 
 	/* Start LTSSM. */
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
-			IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
+			IMX6Q_GPR12_PCIE_CTL_2,
+			IMX6Q_GPR12_PCIE_CTL_2);
 
 	ret = imx6_pcie_wait_for_link(pp);
 	if (ret)
@@ -422,13 +486,19 @@ static int imx6_pcie_start_link(struct pcie_port *pp)
 	return ret;
 }
 
-static void imx6_pcie_host_init(struct pcie_port *pp)
+static int imx6_pcie_host_init(struct pcie_port *pp)
 {
+	int ret;
+
 	imx6_pcie_assert_core_reset(pp);
 
-	imx6_pcie_init_phy(pp);
+	ret = imx6_pcie_init_phy(pp);
+	if (ret < 0)
+		return ret;
 
-	imx6_pcie_deassert_core_reset(pp);
+	ret = imx6_pcie_deassert_core_reset(pp);
+	if (ret < 0)
+		return ret;
 
 	dw_pcie_setup_rc(pp);
 
@@ -436,6 +506,8 @@ static void imx6_pcie_host_init(struct pcie_port *pp)
 
 	if (IS_ENABLED(CONFIG_PCI_MSI))
 		dw_pcie_msi_init(pp);
+
+	return 0;
 }
 
 static void imx6_pcie_reset_phy(struct pcie_port *pp)
@@ -553,6 +625,75 @@ static int __init imx6_add_pcie_port(struct pcie_port *pp,
 	return 0;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int pci_imx_suspend_noirq(struct device *dev)
+{
+	struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
+	struct pcie_port *pp = &imx6_pcie->pp;
+
+	if (is_imx6sx_pcie(imx6_pcie)) {
+		if (IS_ENABLED(CONFIG_PCI_MSI))
+			dw_pcie_msi_cfg_store(pp);
+
+		/* PM_TURN_OFF */
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				IMX6SX_GPR12_PCIE_PM_TURN_OFF,
+				IMX6SX_GPR12_PCIE_PM_TURN_OFF);
+		udelay(10);
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
+		clk_disable_unprepare(imx6_pcie->pcie);
+		clk_disable_unprepare(imx6_pcie->pcie_bus);
+		clk_disable_unprepare(imx6_pcie->pcie_phy);
+		clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
+	}
+
+	return 0;
+}
+
+static int pci_imx_resume_noirq(struct device *dev)
+{
+	struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
+	struct pcie_port *pp = &imx6_pcie->pp;
+
+	if (is_imx6sx_pcie(imx6_pcie)) {
+		clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
+		clk_prepare_enable(imx6_pcie->pcie_bus);
+		clk_prepare_enable(imx6_pcie->pcie_phy);
+		clk_prepare_enable(imx6_pcie->pcie);
+
+		/* Reset iMX6SX PCIe */
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+				IMX6SX_GPR5_PCIE_PERST, IMX6SX_GPR5_PCIE_PERST);
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+				IMX6SX_GPR5_PCIE_PERST, 0);
+		/*
+		 * controller maybe turn off, re-configure again
+		 */
+		dw_pcie_setup_rc(pp);
+
+		if (IS_ENABLED(CONFIG_PCI_MSI))
+			dw_pcie_msi_cfg_restore(pp);
+
+		/* RESET EP */
+		gpio_set_value(imx6_pcie->reset_gpio, 0);
+		udelay(10);
+		gpio_set_value(imx6_pcie->reset_gpio, 1);
+	}
+
+	return 0;
+}
+
+static const struct dev_pm_ops pci_imx_pm_ops = {
+	.suspend_noirq = pci_imx_suspend_noirq,
+	.resume_noirq = pci_imx_resume_noirq,
+	.freeze_noirq = pci_imx_suspend_noirq,
+	.thaw_noirq = pci_imx_resume_noirq,
+	.poweroff_noirq = pci_imx_suspend_noirq,
+	.restore_noirq = pci_imx_resume_noirq,
+};
+#endif
+
 static int __init imx6_pcie_probe(struct platform_device *pdev)
 {
 	struct imx6_pcie *imx6_pcie;
@@ -610,9 +751,28 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
 		return PTR_ERR(imx6_pcie->pcie);
 	}
 
-	/* Grab GPR config register range */
-	imx6_pcie->iomuxc_gpr =
-		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+	if (is_imx6sx_pcie(imx6_pcie)) {
+		imx6_pcie->pcie_inbound_axi = devm_clk_get(&pdev->dev,
+				"pcie_inbound_axi");
+		if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
+			dev_err(&pdev->dev,
+				"pcie clock source missing or invalid\n");
+			return PTR_ERR(imx6_pcie->pcie_inbound_axi);
+		}
+
+		imx6_pcie->pcie_phy_regulator = devm_regulator_get(pp->dev,
+				"pcie-phy");
+
+		imx6_pcie->iomuxc_gpr =
+			 syscon_regmap_lookup_by_compatible
+			 ("fsl,imx6sx-iomuxc-gpr");
+		imx6_pcie->gpc_ips_reg =
+			 syscon_regmap_lookup_by_compatible("fsl,imx6sx-gpc");
+	} else {
+		imx6_pcie->iomuxc_gpr =
+			syscon_regmap_lookup_by_compatible
+			("fsl,imx6q-iomuxc-gpr");
+	}
 	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
 		dev_err(&pdev->dev, "unable to find iomuxc registers\n");
 		return PTR_ERR(imx6_pcie->iomuxc_gpr);
@@ -636,6 +796,7 @@ static void imx6_pcie_shutdown(struct platform_device *pdev)
 
 static const struct of_device_id imx6_pcie_of_match[] = {
 	{ .compatible = "fsl,imx6q-pcie", },
+	{ .compatible = "fsl,imx6sx-pcie", },
 	{},
 };
 MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
@@ -645,6 +806,7 @@ static struct platform_driver imx6_pcie_driver = {
 		.name	= "imx6q-pcie",
 		.owner	= THIS_MODULE,
 		.of_match_table = imx6_pcie_of_match,
+		.pm = &pci_imx_pm_ops,
 	},
 	.shutdown = imx6_pcie_shutdown,
 };
-- 
1.9.1

Re: [PATCH v6 09/13] PCI: imx6: Add imx6sx pcie support

[Lucas Stach]

Am Donnerstag, den 16.10.2014, 15:52 +0800 schrieb Richard Zhu:
> From: Richard Zhu <r65037@freescale.com>
> 
> - imx6sx pcie has its own standalone pcie power supply.
> In order to turn on the imx6sx pcie power during
> initialization. Add the pcie regulator and the gpc regmap
> into the imx6sx pcie structure.
> - imx6sx pcie has the new added reset mechanism, add the
> reset operations into the initialization.
> - register one PM call-back, enter/exit L2 state during
> system suspend/resume.
> use noirq pm_ops instead of the general pm_ops in dev_pm_ops,
> since cfg read/write may occurs after suspend and before resume.
> do msi store/re-store in suspend/resume callbacks, since
> controller maybe turned off, and these msi cfg maybe lost
> in suspend.
> - disp_axi clock is required by pcie inbound axi port actually.
> Add one more clock named pcie_inbound_axi for imx6sx pcie.
> - host init maybe failed, return negative value when
> there is a failure in the host init.
> 
> Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
> ---
>  drivers/pci/host/pci-imx6.c | 204 +++++++++++++++++++++++++++++++++++++++-----
>  1 file changed, 183 insertions(+), 21 deletions(-)
> 
[...]
>  
> +#ifdef CONFIG_PM_SLEEP
> +static int pci_imx_suspend_noirq(struct device *dev)
> +{
> +	struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
> +	struct pcie_port *pp = &imx6_pcie->pp;
> +
> +	if (is_imx6sx_pcie(imx6_pcie)) {
> +		if (IS_ENABLED(CONFIG_PCI_MSI))
> +			dw_pcie_msi_cfg_store(pp);
> +
> +		/* PM_TURN_OFF */
> +		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> +				IMX6SX_GPR12_PCIE_PM_TURN_OFF,
> +				IMX6SX_GPR12_PCIE_PM_TURN_OFF);
> +		udelay(10);
> +		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> +				IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
> +		clk_disable_unprepare(imx6_pcie->pcie);
> +		clk_disable_unprepare(imx6_pcie->pcie_bus);
> +		clk_disable_unprepare(imx6_pcie->pcie_phy);
> +		clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
> +	}
> +
> +	return 0;
> +}
> +
> +static int pci_imx_resume_noirq(struct device *dev)
> +{
> +	struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
> +	struct pcie_port *pp = &imx6_pcie->pp;
> +
> +	if (is_imx6sx_pcie(imx6_pcie)) {
> +		clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
> +		clk_prepare_enable(imx6_pcie->pcie_bus);
> +		clk_prepare_enable(imx6_pcie->pcie_phy);
> +		clk_prepare_enable(imx6_pcie->pcie);
> +
> +		/* Reset iMX6SX PCIe */
> +		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
> +				IMX6SX_GPR5_PCIE_PERST, IMX6SX_GPR5_PCIE_PERST);
> +		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
> +				IMX6SX_GPR5_PCIE_PERST, 0);
> +		/*
> +		 * controller maybe turn off, re-configure again
> +		 */
> +		dw_pcie_setup_rc(pp);
> +
> +		if (IS_ENABLED(CONFIG_PCI_MSI))
> +			dw_pcie_msi_cfg_restore(pp);
> +
> +		/* RESET EP */
> +		gpio_set_value(imx6_pcie->reset_gpio, 0);
> +		udelay(10);

You are violating the spec here: "When PERST# is asserted it must remain
active for a minimum of 100 us (Tperst)." Also you probably want to put
the EP in reset at suspend and only release the reset in the resume
path.

> +		gpio_set_value(imx6_pcie->reset_gpio, 1);
> +	}
> +
> +	return 0;
> +}
> +
> +static const struct dev_pm_ops pci_imx_pm_ops = {
> +	.suspend_noirq = pci_imx_suspend_noirq,
> +	.resume_noirq = pci_imx_resume_noirq,
> +	.freeze_noirq = pci_imx_suspend_noirq,
> +	.thaw_noirq = pci_imx_resume_noirq,
> +	.poweroff_noirq = pci_imx_suspend_noirq,
> +	.restore_noirq = pci_imx_resume_noirq,
> +};
> +#endif
> +
>  static int __init imx6_pcie_probe(struct platform_device *pdev)
>  {
>  	struct imx6_pcie *imx6_pcie;
> @@ -610,9 +751,28 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
>  		return PTR_ERR(imx6_pcie->pcie);
>  	}
>  
> -	/* Grab GPR config register range */
> -	imx6_pcie->iomuxc_gpr =
> -		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
> +	if (is_imx6sx_pcie(imx6_pcie)) {
> +		imx6_pcie->pcie_inbound_axi = devm_clk_get(&pdev->dev,
> +				"pcie_inbound_axi");
> +		if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
> +			dev_err(&pdev->dev,
> +				"pcie clock source missing or invalid\n");
> +			return PTR_ERR(imx6_pcie->pcie_inbound_axi);
> +		}
> +
> +		imx6_pcie->pcie_phy_regulator = devm_regulator_get(pp->dev,
> +				"pcie-phy");
> +
> +		imx6_pcie->iomuxc_gpr =
> +			 syscon_regmap_lookup_by_compatible
> +			 ("fsl,imx6sx-iomuxc-gpr");
> +		imx6_pcie->gpc_ips_reg =
> +			 syscon_regmap_lookup_by_compatible("fsl,imx6sx-gpc");
> +	} else {
> +		imx6_pcie->iomuxc_gpr =
> +			syscon_regmap_lookup_by_compatible
> +			("fsl,imx6q-iomuxc-gpr");
> +	}
>  	if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
>  		dev_err(&pdev->dev, "unable to find iomuxc registers\n");
>  		return PTR_ERR(imx6_pcie->iomuxc_gpr);
> @@ -636,6 +796,7 @@ static void imx6_pcie_shutdown(struct platform_device *pdev)
>  
>  static const struct of_device_id imx6_pcie_of_match[] = {
>  	{ .compatible = "fsl,imx6q-pcie", },
> +	{ .compatible = "fsl,imx6sx-pcie", },
>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
> @@ -645,6 +806,7 @@ static struct platform_driver imx6_pcie_driver = {
>  		.name	= "imx6q-pcie",
>  		.owner	= THIS_MODULE,
>  		.of_match_table = imx6_pcie_of_match,
> +		.pm = &pci_imx_pm_ops,
>  	},
>  	.shutdown = imx6_pcie_shutdown,
>  };

RE: [PATCH v6 09/13] PCI: imx6: Add imx6sx pcie support

[Hong-Xing.Zhu]

DQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IEx1Y2FzIFN0YWNoIFttYWls
dG86bC5zdGFjaEBwZW5ndXRyb25peC5kZV0NCj4gU2VudDogVGh1cnNkYXksIE9jdG9iZXIgMTYs
IDIwMTQgNjo1NCBQTQ0KPiBUbzogUmljaGFyZCBaaHUNCj4gQ2M6IGxpbnV4LXBjaUB2Z2VyLmtl
cm5lbC5vcmc7IEd1byBTaGF3bi1SNjUwNzM7IGZlc3RldmFtQGdtYWlsLmNvbTsNCj4gdGhhcnZl
eUBnYXRld29ya3MuY29tOyBaaHUgUmljaGFyZC1SNjUwMzcNCj4gU3ViamVjdDogUmU6IFtQQVRD
SCB2NiAwOS8xM10gUENJOiBpbXg2OiBBZGQgaW14NnN4IHBjaWUgc3VwcG9ydA0KPiANCj4gQW0g
RG9ubmVyc3RhZywgZGVuIDE2LjEwLjIwMTQsIDE1OjUyICswODAwIHNjaHJpZWIgUmljaGFyZCBa
aHU6DQo+ID4gRnJvbTogUmljaGFyZCBaaHUgPHI2NTAzN0BmcmVlc2NhbGUuY29tPg0KPiA+DQo+
ID4gLSBpbXg2c3ggcGNpZSBoYXMgaXRzIG93biBzdGFuZGFsb25lIHBjaWUgcG93ZXIgc3VwcGx5
Lg0KPiA+IEluIG9yZGVyIHRvIHR1cm4gb24gdGhlIGlteDZzeCBwY2llIHBvd2VyIGR1cmluZyBp
bml0aWFsaXphdGlvbi4gQWRkDQo+ID4gdGhlIHBjaWUgcmVndWxhdG9yIGFuZCB0aGUgZ3BjIHJl
Z21hcCBpbnRvIHRoZSBpbXg2c3ggcGNpZSBzdHJ1Y3R1cmUuDQo+ID4gLSBpbXg2c3ggcGNpZSBo
YXMgdGhlIG5ldyBhZGRlZCByZXNldCBtZWNoYW5pc20sIGFkZCB0aGUgcmVzZXQNCj4gPiBvcGVy
YXRpb25zIGludG8gdGhlIGluaXRpYWxpemF0aW9uLg0KPiA+IC0gcmVnaXN0ZXIgb25lIFBNIGNh
bGwtYmFjaywgZW50ZXIvZXhpdCBMMiBzdGF0ZSBkdXJpbmcgc3lzdGVtDQo+ID4gc3VzcGVuZC9y
ZXN1bWUuDQo+ID4gdXNlIG5vaXJxIHBtX29wcyBpbnN0ZWFkIG9mIHRoZSBnZW5lcmFsIHBtX29w
cyBpbiBkZXZfcG1fb3BzLCBzaW5jZQ0KPiA+IGNmZyByZWFkL3dyaXRlIG1heSBvY2N1cnMgYWZ0
ZXIgc3VzcGVuZCBhbmQgYmVmb3JlIHJlc3VtZS4NCj4gPiBkbyBtc2kgc3RvcmUvcmUtc3RvcmUg
aW4gc3VzcGVuZC9yZXN1bWUgY2FsbGJhY2tzLCBzaW5jZSBjb250cm9sbGVyDQo+ID4gbWF5YmUg
dHVybmVkIG9mZiwgYW5kIHRoZXNlIG1zaSBjZmcgbWF5YmUgbG9zdCBpbiBzdXNwZW5kLg0KPiA+
IC0gZGlzcF9heGkgY2xvY2sgaXMgcmVxdWlyZWQgYnkgcGNpZSBpbmJvdW5kIGF4aSBwb3J0IGFj
dHVhbGx5Lg0KPiA+IEFkZCBvbmUgbW9yZSBjbG9jayBuYW1lZCBwY2llX2luYm91bmRfYXhpIGZv
ciBpbXg2c3ggcGNpZS4NCj4gPiAtIGhvc3QgaW5pdCBtYXliZSBmYWlsZWQsIHJldHVybiBuZWdh
dGl2ZSB2YWx1ZSB3aGVuIHRoZXJlIGlzIGENCj4gPiBmYWlsdXJlIGluIHRoZSBob3N0IGluaXQu
DQo+ID4NCj4gPiBTaWduZWQtb2ZmLWJ5OiBSaWNoYXJkIFpodSA8cmljaGFyZC56aHVAZnJlZXNj
YWxlLmNvbT4NCj4gPiAtLS0NCj4gPiAgZHJpdmVycy9wY2kvaG9zdC9wY2ktaW14Ni5jIHwgMjA0
DQo+ID4gKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrLS0tLS0NCj4gPiAg
MSBmaWxlIGNoYW5nZWQsIDE4MyBpbnNlcnRpb25zKCspLCAyMSBkZWxldGlvbnMoLSkNCj4gPg0K
PiBbLi4uXQ0KPiA+DQo+ID4gKyNpZmRlZiBDT05GSUdfUE1fU0xFRVANCj4gPiArc3RhdGljIGlu
dCBwY2lfaW14X3N1c3BlbmRfbm9pcnEoc3RydWN0IGRldmljZSAqZGV2KSB7DQo+ID4gKwlzdHJ1
Y3QgaW14Nl9wY2llICppbXg2X3BjaWUgPSBkZXZfZ2V0X2RydmRhdGEoZGV2KTsNCj4gPiArCXN0
cnVjdCBwY2llX3BvcnQgKnBwID0gJmlteDZfcGNpZS0+cHA7DQo+ID4gKw0KPiA+ICsJaWYgKGlz
X2lteDZzeF9wY2llKGlteDZfcGNpZSkpIHsNCj4gPiArCQlpZiAoSVNfRU5BQkxFRChDT05GSUdf
UENJX01TSSkpDQo+ID4gKwkJCWR3X3BjaWVfbXNpX2NmZ19zdG9yZShwcCk7DQo+ID4gKw0KPiA+
ICsJCS8qIFBNX1RVUk5fT0ZGICovDQo+ID4gKwkJcmVnbWFwX3VwZGF0ZV9iaXRzKGlteDZfcGNp
ZS0+aW9tdXhjX2dwciwgSU9NVVhDX0dQUjEyLA0KPiA+ICsJCQkJSU1YNlNYX0dQUjEyX1BDSUVf
UE1fVFVSTl9PRkYsDQo+ID4gKwkJCQlJTVg2U1hfR1BSMTJfUENJRV9QTV9UVVJOX09GRik7DQo+
ID4gKwkJdWRlbGF5KDEwKTsNCj4gPiArCQlyZWdtYXBfdXBkYXRlX2JpdHMoaW14Nl9wY2llLT5p
b211eGNfZ3ByLCBJT01VWENfR1BSMTIsDQo+ID4gKwkJCQlJTVg2U1hfR1BSMTJfUENJRV9QTV9U
VVJOX09GRiwgMCk7DQo+ID4gKwkJY2xrX2Rpc2FibGVfdW5wcmVwYXJlKGlteDZfcGNpZS0+cGNp
ZSk7DQo+ID4gKwkJY2xrX2Rpc2FibGVfdW5wcmVwYXJlKGlteDZfcGNpZS0+cGNpZV9idXMpOw0K
PiA+ICsJCWNsa19kaXNhYmxlX3VucHJlcGFyZShpbXg2X3BjaWUtPnBjaWVfcGh5KTsNCj4gPiAr
CQljbGtfZGlzYWJsZV91bnByZXBhcmUoaW14Nl9wY2llLT5wY2llX2luYm91bmRfYXhpKTsNCj4g
PiArCX0NCj4gPiArDQo+ID4gKwlyZXR1cm4gMDsNCj4gPiArfQ0KPiA+ICsNCj4gPiArc3RhdGlj
IGludCBwY2lfaW14X3Jlc3VtZV9ub2lycShzdHJ1Y3QgZGV2aWNlICpkZXYpIHsNCj4gPiArCXN0
cnVjdCBpbXg2X3BjaWUgKmlteDZfcGNpZSA9IGRldl9nZXRfZHJ2ZGF0YShkZXYpOw0KPiA+ICsJ
c3RydWN0IHBjaWVfcG9ydCAqcHAgPSAmaW14Nl9wY2llLT5wcDsNCj4gPiArDQo+ID4gKwlpZiAo
aXNfaW14NnN4X3BjaWUoaW14Nl9wY2llKSkgew0KPiA+ICsJCWNsa19wcmVwYXJlX2VuYWJsZShp
bXg2X3BjaWUtPnBjaWVfaW5ib3VuZF9heGkpOw0KPiA+ICsJCWNsa19wcmVwYXJlX2VuYWJsZShp
bXg2X3BjaWUtPnBjaWVfYnVzKTsNCj4gPiArCQljbGtfcHJlcGFyZV9lbmFibGUoaW14Nl9wY2ll
LT5wY2llX3BoeSk7DQo+ID4gKwkJY2xrX3ByZXBhcmVfZW5hYmxlKGlteDZfcGNpZS0+cGNpZSk7
DQo+ID4gKw0KPiA+ICsJCS8qIFJlc2V0IGlNWDZTWCBQQ0llICovDQo+ID4gKwkJcmVnbWFwX3Vw
ZGF0ZV9iaXRzKGlteDZfcGNpZS0+aW9tdXhjX2dwciwgSU9NVVhDX0dQUjUsDQo+ID4gKwkJCQlJ
TVg2U1hfR1BSNV9QQ0lFX1BFUlNULCBJTVg2U1hfR1BSNV9QQ0lFX1BFUlNUKTsNCj4gPiArCQly
ZWdtYXBfdXBkYXRlX2JpdHMoaW14Nl9wY2llLT5pb211eGNfZ3ByLCBJT01VWENfR1BSNSwNCj4g
PiArCQkJCUlNWDZTWF9HUFI1X1BDSUVfUEVSU1QsIDApOw0KPiA+ICsJCS8qDQo+ID4gKwkJICog
Y29udHJvbGxlciBtYXliZSB0dXJuIG9mZiwgcmUtY29uZmlndXJlIGFnYWluDQo+ID4gKwkJICov
DQo+ID4gKwkJZHdfcGNpZV9zZXR1cF9yYyhwcCk7DQo+ID4gKw0KPiA+ICsJCWlmIChJU19FTkFC
TEVEKENPTkZJR19QQ0lfTVNJKSkNCj4gPiArCQkJZHdfcGNpZV9tc2lfY2ZnX3Jlc3RvcmUocHAp
Ow0KPiA+ICsNCj4gPiArCQkvKiBSRVNFVCBFUCAqLw0KPiA+ICsJCWdwaW9fc2V0X3ZhbHVlKGlt
eDZfcGNpZS0+cmVzZXRfZ3BpbywgMCk7DQo+ID4gKwkJdWRlbGF5KDEwKTsNCj4gDQo+IFlvdSBh
cmUgdmlvbGF0aW5nIHRoZSBzcGVjIGhlcmU6ICJXaGVuIFBFUlNUIyBpcyBhc3NlcnRlZCBpdCBt
dXN0IHJlbWFpbg0KPiBhY3RpdmUgZm9yIGEgbWluaW11bSBvZiAxMDAgdXMgKFRwZXJzdCkuIiBB
bHNvIHlvdSBwcm9iYWJseSB3YW50IHRvIHB1dCB0aGUgRVANCj4gaW4gcmVzZXQgYXQgc3VzcGVu
ZCBhbmQgb25seSByZWxlYXNlIHRoZSByZXNldCBpbiB0aGUgcmVzdW1lIHBhdGguDQo+IA0KW1Jp
Y2hhcmRdIE9vcHMsIHNvcnJ5LiBXb3VsZCBiZSBjaGFuZ2VkIGltbWVkaWF0ZWx5Lg0KQXNzZXJ0
IHRoZSBQRVJTVCMgaW4gc3VzcGVuZCwgYW5kIGRlLWFzc2VydCBpdCBpbiByZXN1bWUuDQpUaGFu
a3MgYSBsb3QgZm9yIHlvdXIgZGV0YWlsZWQgcmV2aWV3Lg0KDQo+ID4gKwkJZ3Bpb19zZXRfdmFs
dWUoaW14Nl9wY2llLT5yZXNldF9ncGlvLCAxKTsNCj4gPiArCX0NCj4gPiArDQo+ID4gKwlyZXR1
cm4gMDsNCj4gPiArfQ0KPiA+ICsNCj4gPiArc3RhdGljIGNvbnN0IHN0cnVjdCBkZXZfcG1fb3Bz
IHBjaV9pbXhfcG1fb3BzID0gew0KPiA+ICsJLnN1c3BlbmRfbm9pcnEgPSBwY2lfaW14X3N1c3Bl
bmRfbm9pcnEsDQo+ID4gKwkucmVzdW1lX25vaXJxID0gcGNpX2lteF9yZXN1bWVfbm9pcnEsDQo+
ID4gKwkuZnJlZXplX25vaXJxID0gcGNpX2lteF9zdXNwZW5kX25vaXJxLA0KPiA+ICsJLnRoYXdf
bm9pcnEgPSBwY2lfaW14X3Jlc3VtZV9ub2lycSwNCj4gPiArCS5wb3dlcm9mZl9ub2lycSA9IHBj
aV9pbXhfc3VzcGVuZF9ub2lycSwNCj4gPiArCS5yZXN0b3JlX25vaXJxID0gcGNpX2lteF9yZXN1
bWVfbm9pcnEsIH07ICNlbmRpZg0KPiA+ICsNCj4gPiAgc3RhdGljIGludCBfX2luaXQgaW14Nl9w
Y2llX3Byb2JlKHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpICB7DQo+ID4gIAlzdHJ1Y3Qg
aW14Nl9wY2llICppbXg2X3BjaWU7DQo+ID4gQEAgLTYxMCw5ICs3NTEsMjggQEAgc3RhdGljIGlu
dCBfX2luaXQgaW14Nl9wY2llX3Byb2JlKHN0cnVjdA0KPiBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYp
DQo+ID4gIAkJcmV0dXJuIFBUUl9FUlIoaW14Nl9wY2llLT5wY2llKTsNCj4gPiAgCX0NCj4gPg0K
PiA+IC0JLyogR3JhYiBHUFIgY29uZmlnIHJlZ2lzdGVyIHJhbmdlICovDQo+ID4gLQlpbXg2X3Bj
aWUtPmlvbXV4Y19ncHIgPQ0KPiA+IC0JCSBzeXNjb25fcmVnbWFwX2xvb2t1cF9ieV9jb21wYXRp
YmxlKCJmc2wsaW14NnEtaW9tdXhjLWdwciIpOw0KPiA+ICsJaWYgKGlzX2lteDZzeF9wY2llKGlt
eDZfcGNpZSkpIHsNCj4gPiArCQlpbXg2X3BjaWUtPnBjaWVfaW5ib3VuZF9heGkgPSBkZXZtX2Ns
a19nZXQoJnBkZXYtPmRldiwNCj4gPiArCQkJCSJwY2llX2luYm91bmRfYXhpIik7DQo+ID4gKwkJ
aWYgKElTX0VSUihpbXg2X3BjaWUtPnBjaWVfaW5ib3VuZF9heGkpKSB7DQo+ID4gKwkJCWRldl9l
cnIoJnBkZXYtPmRldiwNCj4gPiArCQkJCSJwY2llIGNsb2NrIHNvdXJjZSBtaXNzaW5nIG9yIGlu
dmFsaWRcbiIpOw0KPiA+ICsJCQlyZXR1cm4gUFRSX0VSUihpbXg2X3BjaWUtPnBjaWVfaW5ib3Vu
ZF9heGkpOw0KPiA+ICsJCX0NCj4gPiArDQo+ID4gKwkJaW14Nl9wY2llLT5wY2llX3BoeV9yZWd1
bGF0b3IgPSBkZXZtX3JlZ3VsYXRvcl9nZXQocHAtPmRldiwNCj4gPiArCQkJCSJwY2llLXBoeSIp
Ow0KPiA+ICsNCj4gPiArCQlpbXg2X3BjaWUtPmlvbXV4Y19ncHIgPQ0KPiA+ICsJCQkgc3lzY29u
X3JlZ21hcF9sb29rdXBfYnlfY29tcGF0aWJsZQ0KPiA+ICsJCQkgKCJmc2wsaW14NnN4LWlvbXV4
Yy1ncHIiKTsNCj4gPiArCQlpbXg2X3BjaWUtPmdwY19pcHNfcmVnID0NCj4gPiArCQkJIHN5c2Nv
bl9yZWdtYXBfbG9va3VwX2J5X2NvbXBhdGlibGUoImZzbCxpbXg2c3gtZ3BjIik7DQo+ID4gKwl9
IGVsc2Ugew0KPiA+ICsJCWlteDZfcGNpZS0+aW9tdXhjX2dwciA9DQo+ID4gKwkJCXN5c2Nvbl9y
ZWdtYXBfbG9va3VwX2J5X2NvbXBhdGlibGUNCj4gPiArCQkJKCJmc2wsaW14NnEtaW9tdXhjLWdw
ciIpOw0KPiA+ICsJfQ0KPiA+ICAJaWYgKElTX0VSUihpbXg2X3BjaWUtPmlvbXV4Y19ncHIpKSB7
DQo+ID4gIAkJZGV2X2VycigmcGRldi0+ZGV2LCAidW5hYmxlIHRvIGZpbmQgaW9tdXhjIHJlZ2lz
dGVyc1xuIik7DQo+ID4gIAkJcmV0dXJuIFBUUl9FUlIoaW14Nl9wY2llLT5pb211eGNfZ3ByKTsg
QEAgLTYzNiw2ICs3OTYsNyBAQCBzdGF0aWMNCj4gPiB2b2lkIGlteDZfcGNpZV9zaHV0ZG93bihz
dHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQ0KPiA+DQo+ID4gIHN0YXRpYyBjb25zdCBzdHJ1
Y3Qgb2ZfZGV2aWNlX2lkIGlteDZfcGNpZV9vZl9tYXRjaFtdID0gew0KPiA+ICAJeyAuY29tcGF0
aWJsZSA9ICJmc2wsaW14NnEtcGNpZSIsIH0sDQo+ID4gKwl7IC5jb21wYXRpYmxlID0gImZzbCxp
bXg2c3gtcGNpZSIsIH0sDQo+ID4gIAl7fSwNCj4gPiAgfTsNCj4gPiAgTU9EVUxFX0RFVklDRV9U
QUJMRShvZiwgaW14Nl9wY2llX29mX21hdGNoKTsgQEAgLTY0NSw2ICs4MDYsNyBAQA0KPiA+IHN0
YXRpYyBzdHJ1Y3QgcGxhdGZvcm1fZHJpdmVyIGlteDZfcGNpZV9kcml2ZXIgPSB7DQo+ID4gIAkJ
Lm5hbWUJPSAiaW14NnEtcGNpZSIsDQo+ID4gIAkJLm93bmVyCT0gVEhJU19NT0RVTEUsDQo+ID4g
IAkJLm9mX21hdGNoX3RhYmxlID0gaW14Nl9wY2llX29mX21hdGNoLA0KPiA+ICsJCS5wbSA9ICZw
Y2lfaW14X3BtX29wcywNCj4gPiAgCX0sDQo+ID4gIAkuc2h1dGRvd24gPSBpbXg2X3BjaWVfc2h1
dGRvd24sDQo+ID4gIH07DQo+IA0KDQoNCkJlc3QgUmVnYXJkcw0KUmljaGFyZCBaaHUNCg==

[PATCH v6 10/13] ARM: imx6qdl: Enable pcie on imx6qdl sabreauto

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

- enable pcie on imx6qdl sabreauto boards.

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 009abd6..d6040a5 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -410,6 +410,10 @@
 	};
 };
 
+&pcie {
+	status = "okay";
+};
+
 &pwm3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm3>;
-- 
1.9.1

[PATCH v6 11/13] ARM: imx6: Update dts and binding for imx6sx pcie

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

- imx6sx pcie phy has its own power regulator. Add the
pcie phy power suppy into im6sx pcie dts and binding.
- in order to align with imx6qdl's pcie dts, re-format
imx6sx pcie dts.
- in order to align with imx6qdl pcie dts format and
keep clean of imx6 pcie driver, keep the pcie phy clock
in imx6sx pcie dts, although it's the parent clk of the
pcie bus clock now, and would be enabled automatically
when pcie bus clock is enabled. secondly, it's
possible that the external osc maybe used as source
of the pcie_bus clk in board design in future.
- disp_axi clock is required by pcie inbound axi port.
Add one more clock named pcie_inbound_axi for imx6sx pcie.

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 .../devicetree/bindings/pci/fsl,imx6q-pcie.txt     |  8 +++++-
 arch/arm/boot/dts/imx6sx.dtsi                      | 32 ++++++++++++----------
 2 files changed, 25 insertions(+), 15 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index 9455fd0..ad81179 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
@@ -4,7 +4,7 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
 and thus inherits all the common properties defined in designware-pcie.txt.
 
 Required properties:
-- compatible: "fsl,imx6q-pcie"
+- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie"
 - reg: base addresse and length of the pcie controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
@@ -13,6 +13,12 @@ Required properties:
 - clock-names: Must include the following additional entries:
 	- "pcie_phy"
 
+Additional required properties for imx6sx-pcie:
+- clock names: Must include the following additional entries:
+	- "pcie_inbound_axi"
+- power supplies:
+	- pcie-phy-supply: regulator used to power the PCIe PHY
+
 Example:
 
 	pcie@0x01000000 {
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index f4b9da6..0dfeade 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -599,9 +599,9 @@
 					anatop-max-voltage = <1450000>;
 				};
 
-				reg_pcie: regulator-vddpcie@140 {
+				reg_pcie_phy: regulator-vddpcie-phy@140 {
 					compatible = "fsl,anatop-regulator";
-					regulator-name = "vddpcie";
+					regulator-name = "vddpcie-phy";
 					regulator-min-microvolt = <725000>;
 					regulator-max-microvolt = <1450000>;
 					anatop-reg-offset = <0x140>;
@@ -1184,24 +1184,28 @@
 
 		pcie: pcie@0x08000000 {
 			compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
-			reg = <0x08ffc000 0x4000>; /* DBI */
+			reg = <0x08ffc000 0x4000>, <0x08f00000 0x80000>;
+			reg-names = "dbi", "config";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-				  /* configuration space */
-			ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
-				  /* downstream I/O */
-				  0x81000000 0 0          0x08f80000 0 0x00010000
-				  /* non-prefetchable memory */
-				  0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
+			ranges = <0x81000000 0 0          0x08f80000 0 0x00010000 /* downstream I/O */
+				  0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
 			num-lanes = <1>;
-			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
-				 <&clks IMX6SX_CLK_PCIE_AXI>,
+			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+			                <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+			                <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+			                <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
 				 <&clks IMX6SX_CLK_LVDS1_OUT>,
+				 <&clks IMX6SX_CLK_PCIE_REF_125M>,
 				 <&clks IMX6SX_CLK_DISPLAY_AXI>;
-			clock-names = "pcie_ref_125m", "pcie_axi",
-				      "lvds_gate", "display_axi";
+			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
+			pcie-phy-supply = <&reg_pcie_phy>;
 			status = "disabled";
 		};
 	};
-- 
1.9.1

[PATCH v6 12/13] ARM: imx6sx: Add syscon into gpc dts

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

In order to manipulate gpc bits for imx6sx
pcie in driver, add syscon into gpc dts

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 arch/arm/boot/dts/imx6sx.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 0dfeade..88d7fd7 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -689,7 +689,8 @@
 			};
 
 			gpc: gpc@020dc000 {
-				compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
+				compatible = "fsl,imx6sx-gpc",
+					     "fsl,imx6q-gpc", "syscon";
 				reg = <0x020dc000 0x4000>;
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 			};
-- 
1.9.1

[PATCH v6 13/13] ARM: imx6sx: Enable pcie on imx6sx sdb board

[Richard Zhu]

From: Richard Zhu <r65037@freescale.com>

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 arch/arm/boot/dts/imx6sx-sdb.dts | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index a3980d9..e28214a 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -90,6 +90,19 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 		};
+
+		reg_pcie: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_pcie_reg>;
+			regulator-name = "MPCIE_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio2 1 0>;
+			regulator-always-on;
+			enable-active-high;
+		};
 	};
 
 	sound {
@@ -251,6 +264,13 @@
 	};
 };
 
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio2 0 0>;
+	status = "okay";
+};
+
 &ssi2 {
 	status = "okay";
 };
@@ -365,6 +385,18 @@
 			>;
 		};
 
+		pinctrl_pcie: pciegrp {
+			fsl,pins = <
+				MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
+			>;
+		};
+
+		pinctrl_pcie_reg: pciereggrp {
+			fsl,pins = <
+				MX6SX_PAD_ENET1_CRS__GPIO2_IO_1	0x10b0
+			>;
+		};
+
 		pinctrl_vcc_sd3: vccsd3grp {
 			fsl,pins = <
 				MX6SX_PAD_KEY_COL1__GPIO2_IO_11		0x17059
-- 
1.9.1