From: Richard Zhu <richard.zhu@freescale.com>
To: <linux-pci@vger.kernel.org>
Cc: <shawn.guo@freescale.com>, <festevam@gmail.com>,
<l.stach@pengutronix.de>, <tharvey@gateworks.com>,
Richard Zhu <r65037@freescale.com>,
Richard Zhu <richard.zhu@freescale.com>
Subject: [PATCH v6 07/13] ARM: imx6sx: Add imx6sx pcie related gpr bits definitions
Date: Thu, 16 Oct 2014 15:52:37 +0800 [thread overview]
Message-ID: <1413445963-24706-8-git-send-email-richard.zhu@freescale.com> (raw)
In-Reply-To: <1413445963-24706-1-git-send-email-richard.zhu@freescale.com>
From: Richard Zhu <r65037@freescale.com>
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index ff44374..3273b87 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -301,6 +301,7 @@
#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12)
#define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4)
+#define IMX6Q_GPR12_LOS_LEVEL_9 (0x9 << 4)
#define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
@@ -395,4 +396,12 @@
#define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
#define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)
+/* For imx6sx iomux gpr register field define */
+#define IMX6SX_GPR5_PCIE_BTNRST BIT(19)
+#define IMX6SX_GPR5_PCIE_PERST BIT(18)
+
+#define IMX6SX_GPR12_PCIE_PM_TURN_OFF BIT(16)
+#define IMX6SX_GPR12_PCIE_TEST_PD BIT(30)
+#define IMX6SX_GPR12_RX_EQ_MASK (0x7 << 0)
+#define IMX6SX_GPR12_RX_EQ_2 (0x2 << 0)
#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
--
1.9.1
next prev parent reply other threads:[~2014-10-16 8:23 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-16 7:52 [PATCH v6]PCI: imx6: enable pcie on imx6sx sdb and imx6qdl sabreauto Richard Zhu
2014-10-16 7:52 ` [PATCH v6 01/13] PCI: designware: Refine setup_rc and add msi data restore Richard Zhu
2014-10-16 10:36 ` Lucas Stach
2014-10-20 5:23 ` Hong-Xing.Zhu
2014-10-16 7:52 ` [PATCH v6 02/13] PCI: designware: Set func type of host init to int Richard Zhu
2014-10-16 10:39 ` Lucas Stach
2014-10-20 5:21 ` Hong-Xing.Zhu
2014-10-16 7:52 ` [PATCH v6 03/13] PCI: dra7xx: Change the func type of host init Richard Zhu
2014-10-16 7:52 ` [PATCH v6 04/13] PCI: exynos: " Richard Zhu
2014-10-16 7:52 ` [PATCH v6 05/13] PCI: spear: " Richard Zhu
2014-10-16 7:52 ` [PATCH v6 06/13] PCI: designware: Fix one potential assignment error of cfg start Richard Zhu
2014-10-16 7:52 ` Richard Zhu [this message]
2014-10-16 7:52 ` [PATCH v6 08/13] PCI: imx6: Wait the clocks to stabilize after ref_en Richard Zhu
2014-10-16 7:52 ` [PATCH v6 09/13] PCI: imx6: Add imx6sx pcie support Richard Zhu
2014-10-16 10:54 ` Lucas Stach
2014-10-17 2:11 ` Hong-Xing.Zhu
2014-10-16 7:52 ` [PATCH v6 10/13] ARM: imx6qdl: Enable pcie on imx6qdl sabreauto Richard Zhu
2014-10-16 7:52 ` [PATCH v6 11/13] ARM: imx6: Update dts and binding for imx6sx pcie Richard Zhu
2014-10-16 7:52 ` [PATCH v6 12/13] ARM: imx6sx: Add syscon into gpc dts Richard Zhu
2014-10-16 7:52 ` [PATCH v6 13/13] ARM: imx6sx: Enable pcie on imx6sx sdb board Richard Zhu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1413445963-24706-8-git-send-email-richard.zhu@freescale.com \
--to=richard.zhu@freescale.com \
--cc=festevam@gmail.com \
--cc=l.stach@pengutronix.de \
--cc=linux-pci@vger.kernel.org \
--cc=r65037@freescale.com \
--cc=shawn.guo@freescale.com \
--cc=tharvey@gateworks.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).