From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wi0-f180.google.com ([209.85.212.180]:52501 "EHLO mail-wi0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932319AbaKSQFn (ORCPT ); Wed, 19 Nov 2014 11:05:43 -0500 Received: by mail-wi0-f180.google.com with SMTP id n3so2430983wiv.1 for ; Wed, 19 Nov 2014 08:05:42 -0800 (PST) From: Tomasz Nowicki To: catalin.marinas@arm.com, will.deacon@arm.com, bhelgaas@google.com, lorenzo.pieralisi@arm.com, wangyijing@huawei.com, arnd@arndb.de, hanjun.guo@linaro.org, Liviu.Dudau@arm.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, rjw@rjwysocki.net Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, x86@kernel.org, linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, linaro-acpi@lists.linaro.org, Tomasz Nowicki Subject: [PATCH 6/6] pci, acpi: Share ACPI PCI config space accessors. Date: Wed, 19 Nov 2014 17:04:51 +0100 Message-Id: <1416413091-13452-7-git-send-email-tomasz.nowicki@linaro.org> In-Reply-To: <1416413091-13452-1-git-send-email-tomasz.nowicki@linaro.org> References: <1416413091-13452-1-git-send-email-tomasz.nowicki@linaro.org> Sender: linux-pci-owner@vger.kernel.org List-ID: MMCFG can be used perfectly for all architectures which support ACPI. ACPI mandates MMCFG to describe PCI config space ranges which means we should use MMCONFIG accessors by default. Signed-off-by: Tomasz Nowicki Tested-by: Hanjun Guo --- drivers/acpi/mmconfig.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/acpi/mmconfig.c b/drivers/acpi/mmconfig.c index c0ad05f..c9c6e05 100644 --- a/drivers/acpi/mmconfig.c +++ b/drivers/acpi/mmconfig.c @@ -23,6 +23,26 @@ static DEFINE_MUTEX(pci_mmcfg_lock); LIST_HEAD(pci_mmcfg_list); +/* + * raw_pci_read/write - ACPI PCI config space accessors. + * + * ACPI spec defines MMCFG as the way we can access PCI config space, + * so let MMCFG be default (__weak). + * + * If platform needs more fancy stuff, should provides its own implementation. + */ +int __weak raw_pci_read(unsigned int domain, unsigned int bus, + unsigned int devfn, int reg, int len, u32 *val) +{ + return pci_mmcfg_read(domain, bus, devfn, reg, len, val); +} + +int __weak raw_pci_write(unsigned int domain, unsigned int bus, + unsigned int devfn, int reg, int len, u32 val) +{ + return pci_mmcfg_write(domain, bus, devfn, reg, len, val); +} + static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn) { -- 1.9.1