From: Jiang Liu <jiang.liu@linux.intel.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Randy Dunlap <rdunlap@infradead.org>,
Yinghai Lu <yinghai@kernel.org>, Borislav Petkov <bp@alien8.de>,
x86@kernel.org, Jiang Liu <jiang.liu@linux.intel.com>,
Yijing Wang <wangyijing@huawei.com>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
Andrew Morton <akpm@linux-foundation.org>,
Tony Luck <tony.luck@intel.com>, Joerg Roedel <joro@8bytes.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
linux-acpi@vger.kernel.org
Subject: [Patch Part2 v6 18/27] x86, irq: Clean up unused MSI related code and interfaces
Date: Tue, 25 Nov 2014 13:53:27 +0800 [thread overview]
Message-ID: <1416894816-23245-19-git-send-email-jiang.liu@linux.intel.com> (raw)
In-Reply-To: <1416894816-23245-1-git-send-email-jiang.liu@linux.intel.com>
Now MSI interrupt has been converted to new hierarchy irqdomain
interfaces, so kill legacy MSI related code and interfaces.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
---
arch/x86/include/asm/hpet.h | 9 -------
arch/x86/include/asm/x86_init.h | 4 ---
arch/x86/kernel/apic/msi.c | 55 +++------------------------------------
3 files changed, 4 insertions(+), 64 deletions(-)
diff --git a/arch/x86/include/asm/hpet.h b/arch/x86/include/asm/hpet.h
index e87e9faf87a9..5fa9fb0f8809 100644
--- a/arch/x86/include/asm/hpet.h
+++ b/arch/x86/include/asm/hpet.h
@@ -85,15 +85,6 @@ extern struct irq_domain *hpet_create_irq_domain(int hpet_id);
extern int hpet_assign_irq(struct irq_domain *domain,
struct hpet_dev *dev, int dev_num);
-#ifdef CONFIG_PCI_MSI
-extern int default_setup_hpet_msi(unsigned int irq, unsigned int id);
-#else
-static inline int default_setup_hpet_msi(unsigned int irq, unsigned int id)
-{
- return -EINVAL;
-}
-#endif
-
#ifdef CONFIG_HPET_EMULATE_RTC
#include <linux/interrupt.h>
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index f58a9c7a3c86..1649bb9ca27c 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -175,13 +175,9 @@ struct msi_msg;
struct x86_msi_ops {
int (*setup_msi_irqs)(struct pci_dev *dev, int nvec, int type);
- void (*compose_msi_msg)(struct pci_dev *dev, unsigned int irq,
- unsigned int dest, struct msi_msg *msg,
- u8 hpet_id);
void (*teardown_msi_irq)(unsigned int irq);
void (*teardown_msi_irqs)(struct pci_dev *dev);
void (*restore_msi_irqs)(struct pci_dev *dev);
- int (*setup_hpet_msi)(unsigned int irq, unsigned int id);
};
struct IO_APIC_route_entry;
diff --git a/arch/x86/kernel/apic/msi.c b/arch/x86/kernel/apic/msi.c
index fa2dd6ebcaea..afaaa1166a7d 100644
--- a/arch/x86/kernel/apic/msi.c
+++ b/arch/x86/kernel/apic/msi.c
@@ -25,16 +25,12 @@
static struct irq_domain *msi_default_domain;
-void native_compose_msi_msg(struct pci_dev *pdev,
- unsigned int irq, unsigned int dest,
- struct msi_msg *msg, u8 hpet_id)
+static void native_compose_msi_msg(struct irq_cfg *cfg, struct msi_msg *msg)
{
- struct irq_cfg *cfg = irq_cfg(irq);
-
msg->address_hi = MSI_ADDR_BASE_HI;
if (x2apic_enabled())
- msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest);
+ msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
msg->address_lo =
MSI_ADDR_BASE_LO |
@@ -44,7 +40,7 @@ void native_compose_msi_msg(struct pci_dev *pdev,
((apic->irq_delivery_mode != dest_LowestPrio) ?
MSI_ADDR_REDIRECTION_CPU :
MSI_ADDR_REDIRECTION_LOWPRI) |
- MSI_ADDR_DEST_ID(dest);
+ MSI_ADDR_DEST_ID(cfg->dest_apicid);
msg->data =
MSI_DATA_TRIGGER_EDGE |
@@ -93,31 +89,6 @@ static void msi_update_msg(struct msi_msg *msg, struct irq_data *irq_data)
msg->address_lo |= MSI_ADDR_DEST_ID(cfg->dest_apicid);
}
-static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
- struct msi_msg *msg, u8 hpet_id)
-{
- struct irq_cfg *cfg;
- int err;
- unsigned dest;
-
- if (disable_apic)
- return -ENXIO;
-
- cfg = irq_cfg(irq);
- err = assign_irq_vector(irq, cfg, apic->target_cpus());
- if (err)
- return err;
-
- err = apic->cpu_mask_to_apicid_and(cfg->domain,
- apic->target_cpus(), &dest);
- if (err)
- return err;
-
- x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id);
-
- return 0;
-}
-
/*
* IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
* which implement the MSI or MSI-X Capability Structure.
@@ -262,7 +233,7 @@ int arch_setup_dmar_msi(unsigned int irq)
struct msi_msg msg;
struct irq_cfg *cfg = irq_cfg(irq);
- native_compose_msi_msg(NULL, irq, cfg->dest_apicid, &msg, -1);
+ native_compose_msi_msg(cfg, &msg);
dmar_msi_write(irq, &msg);
irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
"edge");
@@ -318,24 +289,6 @@ static struct irq_chip hpet_msi_controller = {
.flags = IRQCHIP_SKIP_SET_WAKE,
};
-int default_setup_hpet_msi(unsigned int irq, unsigned int id)
-{
- struct irq_chip *chip = &hpet_msi_controller;
- struct msi_msg msg;
- int ret;
-
- ret = msi_compose_msg(NULL, irq, &msg, id);
- if (ret < 0)
- return ret;
-
- hpet_msi_write(irq_get_handler_data(irq), &msg);
- irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
- setup_remapped_irq(irq, irq_cfg(irq), chip);
-
- irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
- return 0;
-}
-
static int hpet_domain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
--
1.7.10.4
next prev parent reply other threads:[~2014-11-25 5:53 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-25 5:53 [Patch Part2 v6 00/27] Enable hierarchy irqdomian on x86 platforms Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 01/27] x86, irq: Save destination CPU ID in irq_cfg Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 02/27] x86, irq: Use hierarchy irqdomain to manage CPU interrupt vectors Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 03/27] x86, hpet: Use new irqdomain interfaces to allocate/free IRQ Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 04/27] x86, MSI: " Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 05/27] x86, uv: " Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 06/27] x86, htirq: " Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 07/27] x86, dmar: " Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 08/27] x86: irq_remapping: Introduce new interfaces to support hierarchy irqdomain Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 09/27] iommu/vt-d: Change prototypes to prepare for enabling " Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 10/27] iommu/vt-d: Enhance Intel IR driver to suppport " Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 11/27] iommu/amd: Enhance AMD " Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 12/27] x86, hpet: Enhance HPET IRQ to support " Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 13/27] x86, PCI, MSI: Use hierarchy irqdomain to manage MSI interrupts Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 14/27] x86, irq: Directly call native_compose_msi_msg() for DMAR IRQ Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 15/27] iommu/vt-d: Clean up unused MSI related code Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 16/27] iommu/amd: " Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 17/27] x86: irq_remapping: " Jiang Liu
2014-11-25 5:53 ` Jiang Liu [this message]
2014-11-25 5:53 ` [Patch Part2 v6 19/27] iommu/vt-d: Refine the interfaces to create IRQ for DMAR unit Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 20/27] x86, irq: Use hierarchy irqdomain to manage DMAR interrupts Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 21/27] x86, htirq: Use hierarchy irqdomain to manage Hypertransport interrupts Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 22/27] x86, uv: Use hierarchy irqdomain to manage UV interrupts Jiang Liu
2014-12-15 21:37 ` Dimitri Sivanich
2014-12-16 17:29 ` Dimitri Sivanich
2014-12-17 2:41 ` Jiang Liu
2014-12-17 16:45 ` Russ Anderson
2014-12-23 7:18 ` Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 23/27] x86, irq: Normalize x86 irq_chip name Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 24/27] x86, PCI/MSI: Simplify the way to deal with remapped MSI interrupts Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 25/27] PCI/MSI: Replace msi_update_msg() with irq_chip_compose_msi_msg() Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 26/27] x86, irq: Implement irq_chip.irq_write_msi_msg for MSI/DMAR/HPET irq_chips Jiang Liu
2014-11-25 5:53 ` [Patch Part2 v6 27/27] x86, irq: Simplify MSI/DMAR/HPET implementation by using common code Jiang Liu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1416894816-23245-19-git-send-email-jiang.liu@linux.intel.com \
--to=jiang.liu@linux.intel.com \
--cc=akpm@linux-foundation.org \
--cc=benh@kernel.crashing.org \
--cc=bhelgaas@google.com \
--cc=bp@alien8.de \
--cc=gregkh@linuxfoundation.org \
--cc=hpa@zytor.com \
--cc=joro@8bytes.org \
--cc=konrad.wilk@oracle.com \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=mingo@redhat.com \
--cc=rdunlap@infradead.org \
--cc=rjw@rjwysocki.net \
--cc=tglx@linutronix.de \
--cc=tony.luck@intel.com \
--cc=wangyijing@huawei.com \
--cc=x86@kernel.org \
--cc=yinghai@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).