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From: Jiang Liu <jiang.liu@linux.intel.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Randy Dunlap <rdunlap@infradead.org>,
	Yinghai Lu <yinghai@kernel.org>, Borislav Petkov <bp@alien8.de>,
	x86@kernel.org, Jiang Liu <jiang.liu@linux.intel.com>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	Tony Luck <tony.luck@intel.com>, Joerg Roedel <joro@8bytes.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-acpi@vger.kernel.org
Subject: [Patch Part2 v6 05/27] x86, uv: Use new irqdomain interfaces to allocate/free IRQ
Date: Tue, 25 Nov 2014 13:53:14 +0800	[thread overview]
Message-ID: <1416894816-23245-6-git-send-email-jiang.liu@linux.intel.com> (raw)
In-Reply-To: <1416894816-23245-1-git-send-email-jiang.liu@linux.intel.com>

Use new irqdomain interfaces to allocate/free IRQ, so we could
kill GENERIC_IRQ_LEGACY_ALLOC_HWIRQ later.

Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
---
 arch/x86/platform/uv/uv_irq.c |   27 +++++++++++----------------
 1 file changed, 11 insertions(+), 16 deletions(-)

diff --git a/arch/x86/platform/uv/uv_irq.c b/arch/x86/platform/uv/uv_irq.c
index 0ce673645432..474912d03f40 100644
--- a/arch/x86/platform/uv/uv_irq.c
+++ b/arch/x86/platform/uv/uv_irq.c
@@ -12,6 +12,7 @@
 #include <linux/rbtree.h>
 #include <linux/slab.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 
 #include <asm/apic.h>
 #include <asm/uv/uv_irq.h>
@@ -130,24 +131,14 @@ static int
 arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
 		       unsigned long mmr_offset, int limit)
 {
-	const struct cpumask *eligible_cpu = cpumask_of(cpu);
 	struct irq_cfg *cfg = irq_cfg(irq);
 	unsigned long mmr_value;
 	struct uv_IO_APIC_route_entry *entry;
-	int mmr_pnode, err;
-	unsigned int dest;
+	int mmr_pnode;
 
 	BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) !=
 			sizeof(unsigned long));
 
-	err = assign_irq_vector(irq, cfg, eligible_cpu);
-	if (err != 0)
-		return err;
-
-	err = apic->cpu_mask_to_apicid_and(eligible_cpu, eligible_cpu, &dest);
-	if (err != 0)
-		return err;
-
 	if (limit == UV_AFFINITY_CPU)
 		irq_set_status_flags(irq, IRQ_NO_BALANCING);
 	else
@@ -164,7 +155,7 @@ arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
 	entry->polarity		= 0;
 	entry->trigger		= 0;
 	entry->mask		= 0;
-	entry->dest		= dest;
+	entry->dest		= cfg->dest_apicid;
 
 	mmr_pnode = uv_blade_to_pnode(mmr_blade);
 	uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
@@ -238,9 +229,13 @@ uv_set_irq_affinity(struct irq_data *data, const struct cpumask *mask,
 int uv_setup_irq(char *irq_name, int cpu, int mmr_blade,
 		 unsigned long mmr_offset, int limit)
 {
-	int ret, irq = irq_alloc_hwirq(uv_blade_to_memory_nid(mmr_blade));
+	int ret, irq;
+	struct irq_alloc_info info;
 
-	if (!irq)
+	init_irq_alloc_info(&info, cpumask_of(cpu));
+	irq = irq_domain_alloc_irqs(NULL, 1, uv_blade_to_memory_nid(mmr_blade),
+				    &info);
+	if (irq <= 0)
 		return -EBUSY;
 
 	ret = arch_enable_uv_irq(irq_name, irq, cpu, mmr_blade, mmr_offset,
@@ -248,7 +243,7 @@ int uv_setup_irq(char *irq_name, int cpu, int mmr_blade,
 	if (ret == irq)
 		uv_set_irq_2_mmr_info(irq, mmr_offset, mmr_blade);
 	else
-		irq_free_hwirq(irq);
+		irq_domain_free_irqs(irq, 1);
 
 	return ret;
 }
@@ -283,6 +278,6 @@ void uv_teardown_irq(unsigned int irq)
 			n = n->rb_right;
 	}
 	spin_unlock_irqrestore(&uv_irq_lock, irqflags);
-	irq_free_hwirq(irq);
+	irq_domain_free_irqs(irq, 1);
 }
 EXPORT_SYMBOL_GPL(uv_teardown_irq);
-- 
1.7.10.4


  parent reply	other threads:[~2014-11-25  5:51 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-25  5:53 [Patch Part2 v6 00/27] Enable hierarchy irqdomian on x86 platforms Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 01/27] x86, irq: Save destination CPU ID in irq_cfg Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 02/27] x86, irq: Use hierarchy irqdomain to manage CPU interrupt vectors Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 03/27] x86, hpet: Use new irqdomain interfaces to allocate/free IRQ Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 04/27] x86, MSI: " Jiang Liu
2014-11-25  5:53 ` Jiang Liu [this message]
2014-11-25  5:53 ` [Patch Part2 v6 06/27] x86, htirq: " Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 07/27] x86, dmar: " Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 08/27] x86: irq_remapping: Introduce new interfaces to support hierarchy irqdomain Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 09/27] iommu/vt-d: Change prototypes to prepare for enabling " Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 10/27] iommu/vt-d: Enhance Intel IR driver to suppport " Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 11/27] iommu/amd: Enhance AMD " Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 12/27] x86, hpet: Enhance HPET IRQ to support " Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 13/27] x86, PCI, MSI: Use hierarchy irqdomain to manage MSI interrupts Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 14/27] x86, irq: Directly call native_compose_msi_msg() for DMAR IRQ Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 15/27] iommu/vt-d: Clean up unused MSI related code Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 16/27] iommu/amd: " Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 17/27] x86: irq_remapping: " Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 18/27] x86, irq: Clean up unused MSI related code and interfaces Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 19/27] iommu/vt-d: Refine the interfaces to create IRQ for DMAR unit Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 20/27] x86, irq: Use hierarchy irqdomain to manage DMAR interrupts Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 21/27] x86, htirq: Use hierarchy irqdomain to manage Hypertransport interrupts Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 22/27] x86, uv: Use hierarchy irqdomain to manage UV interrupts Jiang Liu
2014-12-15 21:37   ` Dimitri Sivanich
2014-12-16 17:29     ` Dimitri Sivanich
2014-12-17  2:41       ` Jiang Liu
2014-12-17 16:45         ` Russ Anderson
2014-12-23  7:18           ` Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 23/27] x86, irq: Normalize x86 irq_chip name Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 24/27] x86, PCI/MSI: Simplify the way to deal with remapped MSI interrupts Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 25/27] PCI/MSI: Replace msi_update_msg() with irq_chip_compose_msi_msg() Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 26/27] x86, irq: Implement irq_chip.irq_write_msi_msg for MSI/DMAR/HPET irq_chips Jiang Liu
2014-11-25  5:53 ` [Patch Part2 v6 27/27] x86, irq: Simplify MSI/DMAR/HPET implementation by using common code Jiang Liu

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