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From: Wei Yang <weiyang@linux.vnet.ibm.com>
To: bhelgaas@google.com, benh@au1.ibm.com, gwshan@linux.vnet.ibm.com
Cc: linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
	Wei Yang <weiyang@linux.vnet.ibm.com>
Subject: [PATCH V16 05/20] PCI: Refresh First VF Offset and VF Stride when updating NumVFs
Date: Wed, 25 Mar 2015 16:23:46 +0800	[thread overview]
Message-ID: <1427271841-28749-6-git-send-email-weiyang@linux.vnet.ibm.com> (raw)
In-Reply-To: <1427271841-28749-1-git-send-email-weiyang@linux.vnet.ibm.com>

The First VF Offset and VF Stride fields depend on the NumVFs setting, so
refresh the cached fields in struct pci_sriov when updating NumVFs.  See
the SR-IOV spec r1.1, sec 3.3.9 and 3.3.10.

[bhelgaas: changelog, remove kernel-doc comment marker]
Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
---
 drivers/pci/iov.c |   23 +++++++++++++++++++----
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index 27b98c3..a8752c2 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -31,6 +31,21 @@ static inline u8 virtfn_devfn(struct pci_dev *dev, int id)
 		dev->sriov->stride * id) & 0xff;
 }
 
+/*
+ * Per SR-IOV spec sec 3.3.10 and 3.3.11, First VF Offset and VF Stride may
+ * change when NumVFs changes.
+ *
+ * Update iov->offset and iov->stride when NumVFs is written.
+ */
+static inline void pci_iov_set_numvfs(struct pci_dev *dev, int nr_virtfn)
+{
+	struct pci_sriov *iov = dev->sriov;
+
+	pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, nr_virtfn);
+	pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_OFFSET, &iov->offset);
+	pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_STRIDE, &iov->stride);
+}
+
 static struct pci_bus *virtfn_add_bus(struct pci_bus *bus, int busnr)
 {
 	struct pci_bus *child;
@@ -253,7 +268,7 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
 			return rc;
 	}
 
-	pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, nr_virtfn);
+	pci_iov_set_numvfs(dev, nr_virtfn);
 	iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
 	pci_cfg_access_lock(dev);
 	pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
@@ -282,7 +297,7 @@ failed:
 	iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
 	pci_cfg_access_lock(dev);
 	pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
-	pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, 0);
+	pci_iov_set_numvfs(dev, 0);
 	ssleep(1);
 	pci_cfg_access_unlock(dev);
 
@@ -313,7 +328,7 @@ static void sriov_disable(struct pci_dev *dev)
 		sysfs_remove_link(&dev->dev.kobj, "dep_link");
 
 	iov->num_VFs = 0;
-	pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, 0);
+	pci_iov_set_numvfs(dev, 0);
 }
 
 static int sriov_init(struct pci_dev *dev, int pos)
@@ -452,7 +467,7 @@ static void sriov_restore_state(struct pci_dev *dev)
 		pci_update_resource(dev, i);
 
 	pci_write_config_dword(dev, iov->pos + PCI_SRIOV_SYS_PGSIZE, iov->pgsz);
-	pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, iov->num_VFs);
+	pci_iov_set_numvfs(dev, iov->num_VFs);
 	pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
 	if (iov->ctrl & PCI_SRIOV_CTRL_VFE)
 		msleep(100);
-- 
1.7.9.5


  parent reply	other threads:[~2015-03-25  8:26 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-25  8:23 [PATCH V16 00/20] Enable SRIOV on POWER8 Wei Yang
2015-03-25  8:23 ` [PATCH V16 01/20] PCI: Print more info in sriov_enable() error message Wei Yang
2015-03-25  8:23 ` [PATCH V16 02/20] PCI: Print PF SR-IOV resource that contains all VF(n) BAR space Wei Yang
2015-03-25  8:23 ` [PATCH V16 03/20] PCI: Keep individual VF BAR size in struct pci_sriov Wei Yang
2015-03-25  8:23 ` [PATCH V16 04/20] PCI: Index IOV resources in the conventional style Wei Yang
2015-03-25  8:23 ` Wei Yang [this message]
2015-03-25  8:23 ` [PATCH V16 06/20] PCI: Calculate maximum number of buses required for VFs Wei Yang
2015-03-25  8:23 ` [PATCH V16 07/20] PCI: Export pci_iov_virtfn_bus() and pci_iov_virtfn_devfn() Wei Yang
2015-03-25  8:23 ` [PATCH V16 08/20] PCI: Add pcibios_sriov_enable() and pcibios_sriov_disable() Wei Yang
2015-03-25  8:23 ` [PATCH V16 09/20] PCI: Add pcibios_iov_resource_alignment() interface Wei Yang
2015-03-25  8:23 ` [PATCH V16 10/20] PCI: Consider additional PF's IOV BAR alignment in sizing and assigning Wei Yang
2015-03-25  8:23 ` [PATCH V16 11/20] powerpc/pci: Create pci_dn for VFs Wei Yang
2015-03-25  8:23 ` [PATCH V16 12/20] powerpc/pci: Don't unset PCI resources " Wei Yang
2015-03-25  8:23 ` [PATCH V16 13/20] powerpc/powernv: Allocate struct pnv_ioda_pe iommu_table dynamically Wei Yang
2015-03-25  8:23 ` [PATCH V16 14/20] powerpc/powernv: Reserve additional space for IOV BAR according to the number of total_pe Wei Yang
2015-03-25  8:23 ` [PATCH V16 15/20] powerpc/powernv: Implement pcibios_iov_resource_alignment() on powernv Wei Yang
2015-03-25  8:23 ` [PATCH V16 16/20] powerpc/powernv: Shift VF resource with an offset Wei Yang
2015-03-25  8:23 ` [PATCH V16 17/20] powerpc/powernv: Reserve additional space for IOV BAR, with m64_per_iov supported Wei Yang
2015-03-25  8:23 ` [PATCH V16 18/20] powerpc/powernv: Group VF PE when IOV BAR is big on PHB3 Wei Yang
2015-03-25  8:24 ` [PATCH V16 19/20] powerpc/pci: Remove unused struct pci_dn.pcidev field Wei Yang
2015-03-25  8:24 ` [PATCH V16 20/20] powerpc/pci: Add PCI resource alignment documentation Wei Yang

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