From: Jiang Liu <jiang.liu@linux.intel.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Randy Dunlap <rdunlap@infradead.org>,
Yinghai Lu <yinghai@kernel.org>, Borislav Petkov <bp@alien8.de>,
Dimitri Sivanich <sivanich@sgi.com>,
Joerg Roedel <joro@8bytes.org>
Cc: Jiang Liu <jiang.liu@linux.intel.com>,
Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
David Cohen <david.a.cohen@linux.intel.com>,
Sander Eikelenboom <linux@eikelenboom.it>,
David Vrabel <david.vrabel@citrix.com>,
Andrew Morton <akpm@linux-foundation.org>,
Tony Luck <tony.luck@intel.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
x86@kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org,
iommu@lists.linux-foundation.org
Subject: [Patch Part1 v8 09/37] irq_remapping/vt-d: Change prototypes to prepare for enabling hierarchy irqdomain
Date: Mon, 13 Apr 2015 14:11:31 +0800 [thread overview]
Message-ID: <1428905519-23704-10-git-send-email-jiang.liu@linux.intel.com> (raw)
In-Reply-To: <1428905519-23704-1-git-send-email-jiang.liu@linux.intel.com>
Prepare for support hierarchy irqdomain by changing function prototypes,
should be no function changes.
Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
Acked-by: Joerg Roedel <jroedel@suse.de>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: iommu@lists.linux-foundation.org
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Yinghai Lu <yinghai@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Joerg Roedel <joro@8bytes.org>
Link: http://lkml.kernel.org/r/1416894816-23245-10-git-send-email-jiang.liu@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
drivers/iommu/intel_irq_remapping.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/iommu/intel_irq_remapping.c b/drivers/iommu/intel_irq_remapping.c
index 14de1ab223c8..d3adaf32b3ec 100644
--- a/drivers/iommu/intel_irq_remapping.c
+++ b/drivers/iommu/intel_irq_remapping.c
@@ -82,10 +82,10 @@ static int get_irte(int irq, struct irte *entry)
return 0;
}
-static int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
+static int alloc_irte(struct intel_iommu *iommu, int irq,
+ struct irq_2_iommu *irq_iommu, u16 count)
{
struct ir_table *table = iommu->ir_table;
- struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
struct irq_cfg *cfg = irq_cfg(irq);
unsigned int mask = 0;
unsigned long flags;
@@ -173,9 +173,9 @@ static int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subha
return 0;
}
-static int modify_irte(int irq, struct irte *irte_modified)
+static int modify_irte(struct irq_2_iommu *irq_iommu,
+ struct irte *irte_modified)
{
- struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
struct intel_iommu *iommu;
unsigned long flags;
struct irte *irte;
@@ -242,7 +242,7 @@ static int clear_entries(struct irq_2_iommu *irq_iommu)
return 0;
iommu = irq_iommu->iommu;
- index = irq_iommu->irte_index + irq_iommu->sub_handle;
+ index = irq_iommu->irte_index;
start = iommu->ir_table->base + index;
end = start + (1 << irq_iommu->irte_mask);
@@ -986,7 +986,7 @@ static int intel_setup_ioapic_entry(int irq,
pr_warn("No mapping iommu for ioapic %d\n", ioapic_id);
index = -ENODEV;
} else {
- index = alloc_irte(iommu, irq, 1);
+ index = alloc_irte(iommu, irq, irq_2_iommu(irq), 1);
if (index < 0) {
pr_warn("Failed to allocate IRTE for ioapic %d\n",
ioapic_id);
@@ -1002,7 +1002,7 @@ static int intel_setup_ioapic_entry(int irq,
/* Set source-id of interrupt request */
set_ioapic_sid(&irte, ioapic_id);
- modify_irte(irq, &irte);
+ modify_irte(irq_2_iommu(irq), &irte);
apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
"Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
@@ -1089,7 +1089,7 @@ intel_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
* Atomically updates the IRTE with the new destination, vector
* and flushes the interrupt entry cache.
*/
- modify_irte(irq, &irte);
+ modify_irte(irq_2_iommu(irq), &irte);
/*
* After this point, all the interrupts will start arriving
@@ -1125,7 +1125,7 @@ static void intel_compose_msi_msg(struct pci_dev *pdev,
else
set_hpet_sid(&irte, hpet_id);
- modify_irte(irq, &irte);
+ modify_irte(irq_2_iommu(irq), &irte);
msg->address_hi = MSI_ADDR_BASE_HI;
msg->data = sub_handle;
@@ -1152,7 +1152,7 @@ static int intel_msi_alloc_irq(struct pci_dev *dev, int irq, int nvec)
"Unable to map PCI %s to iommu\n", pci_name(dev));
index = -ENOENT;
} else {
- index = alloc_irte(iommu, irq, nvec);
+ index = alloc_irte(iommu, irq, irq_2_iommu(irq), nvec);
if (index < 0) {
printk(KERN_ERR
"Unable to allocate %d IRTE for PCI %s\n",
@@ -1196,7 +1196,7 @@ static int intel_alloc_hpet_msi(unsigned int irq, unsigned int id)
down_read(&dmar_global_lock);
iommu = map_hpet_to_ir(id);
if (iommu) {
- index = alloc_irte(iommu, irq, 1);
+ index = alloc_irte(iommu, irq, irq_2_iommu(irq), 1);
if (index >= 0)
ret = 0;
}
--
1.7.10.4
next prev parent reply other threads:[~2015-04-13 6:11 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-13 6:11 [Patch Part1 v8 00/37] Convert x86 to hierarchy irqdomain and stacked irqchip Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 01/37] x86/irq: Save destination CPU ID in irq_cfg Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 02/37] x86/irq: Use hierarchy irqdomain to manage CPU interrupt vectors Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 03/37] x86/hpet: Use new irqdomain interfaces to allocate/free IRQ Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 04/37] x86/MSI: " Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 05/37] x86/uv: " Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 06/37] x86/htirq: " Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 07/37] x86/dmar: " Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 08/37] irq_remapping: Introduce new interfaces to support hierarchy irqdomain Jiang Liu
2015-04-13 6:11 ` Jiang Liu [this message]
2015-04-13 6:11 ` [Patch Part1 v8 10/37] irq_remapping/vt-d: Enhance Intel IR driver " Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 11/37] irq_remapping/amd: Enhance AMD " Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 12/37] x86/hpet: Enhance HPET IRQ " Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 13/37] x86/MSI: Use hierarchy irqdomain to manage MSI interrupts Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 14/37] x86/irq: Directly call native_compose_msi_msg() for DMAR IRQ Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 15/37] irq_remapping/vt-d: Clean up unused MSI related code Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 16/37] irq_remapping/amd: " Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 17/37] irq_remapping: " Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 18/37] x86/MSI: Clean up unused MSI related code and interfaces Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 19/37] iommu/vt-d: Refine the interfaces to create IRQ for DMAR unit Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 20/37] x86/irq: Use hierarchy irqdomain to manage DMAR interrupts Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 21/37] x86/htirq: Use hierarchy irqdomain to manage Hypertransport interrupts Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 22/37] x86/uv: Use hierarchy irqdomain to manage UV interrupts Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 23/37] x86/irq: Normalize x86 irq_chip name Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 24/37] x86/MSI: Simplify the way to deal with remapped MSI interrupts Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 25/37] x86/MSI: Replace msi_update_msg() with irq_chip_compose_msi_msg() Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 26/37] x86/irq: Implement irq_chip.irq_write_msi_msg for MSI/DMAR/HPET irq_chips Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 27/37] x86/irq: Simplify MSI/DMAR/HPET implementation by using common code Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 28/37] irq_remapping: Kill unused function irq_remapping_print_chip() Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 29/37] x86/intel-mid: Delay initialization of APB timer Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 30/37] x86/intel-mid, trivial: Refine code syntax for sfi_parse_mtmr() Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 31/37] x86/irq: Kill unused pre_init_apic_IRQ0() Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 32/37] x86/irq: Prepare IOAPIC interfaces to support hierarchy irqdomain Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 33/37] x86/irq: Implement callbacks to enable hierarchy irqdomain on IOAPICs Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 34/37] x86/irq: Refine the way to allocate irq_cfg for legacy IRQs Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 35/37] x86/irq: Simplify the way to print IOAPIC entry Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 36/37] x86/irq: Introduce helper functions to support hierarchy irqdomain for IOAPIC Jiang Liu
2015-04-13 6:11 ` [Patch Part1 v8 37/37] x86/irq: Convert IOAPIC to use hierarchy irqdomain interfaces Jiang Liu
2015-04-13 6:19 ` [Patch Part1 v8 00/37] Convert x86 to hierarchy irqdomain and stacked irqchip Ingo Molnar
2015-04-13 6:23 ` Jiang Liu
2015-04-13 7:09 ` Thomas Gleixner
2015-04-13 12:09 ` Rafael J. Wysocki
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