From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66DA6353A9B for ; Wed, 26 Aug 2026 08:20:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.24 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787732431; cv=none; b=a78VjCKZn7YQrqECqWXP0ytG//xhlvLDL9wToSQa0AyqHjg/1Uo3exnrfdMFgOLVhb1uD36PIGjj9jvoy3DTNWjjcW+gknPsuh9fKQdIiVTGkldKcfpc0VYPn+4fQ4m747sYrBZPbktfvQapfb8/XA30uK9Ba/81BpHtzDecrEc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787732431; c=relaxed/simple; bh=JUGhn3ciuyVu2mSHFfinDG36W5TP4C4RLbQLe1+hNnI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:MIME-Version: Content-Type:References; b=dJAfJxP1SNwsSivNAFgcPYl6sQ3W0TkBkRWdReYfCwjl7iehntHWOl2DOb9+IwYrWG7ritE2w/jqMtjCobk+aZTFIS47oPhpXTba63Mi2TrWupOQxO2NwUufOl7hYU3qFvVNyjMaFpjbAG/t9vhxleyKjtqHmZzuvPwwtfleAxY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=gFH3C+jV; arc=none smtp.client-ip=203.254.224.24 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="gFH3C+jV" Received: from epcas5p4.samsung.com (unknown [182.195.41.42]) by mailout1.samsung.com (KnoxPortal) with ESMTP id 20260826081503epoutp01ebb7918b553d5bf0972a2246af1157e0~PTOBKVTeC0440404404epoutp01j for ; Wed, 26 Aug 2026 08:15:03 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.samsung.com 20260826081503epoutp01ebb7918b553d5bf0972a2246af1157e0~PTOBKVTeC0440404404epoutp01j DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1787732103; bh=4RMhxE2Z3C/IuOSrEbcX8wrMEwxJYWrHoYRnX7Wxa+E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gFH3C+jVpJ0Ei27ZoL2DYY+VsDYYdM8jJ5Fyz2J8Zt0PeWsjzlMQEcXENtVlo3PCk OxQQ9vi6KZSXHgdGRxz/sghZLxJQQ24Q6fU5TwK4oyiUCVMyN0r1vqgHAllZ/Lkrbd hUe0oaOzVJ5skmOo/M0ifORG9CWeLf4Ix1r/KMzA= Received: from epsnrtp04.localdomain (unknown [182.195.42.156]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPS id 20260826081502epcas5p46ea6912ff829d29c19c7b9e2bab7dd4a~PTOArarDO1994519945epcas5p4x; Wed, 26 Aug 2026 08:15:02 +0000 (GMT) Received: from epcpadp1new (unknown [182.195.40.141]) by epsnrtp04.localdomain (Postfix) with ESMTP id 4hVHWV5Bgpz6B9m9; Wed, 26 Aug 2026 08:15:02 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20260826052014epcas5p11846c6a40fcec4ec4ba441ceb26e5dcc~PQ1ZKh1tC0398803988epcas5p1i; Wed, 26 Aug 2026 05:20:14 +0000 (GMT) Received: from unvme-SYS-221H-TN24R.samsungds.net (unknown [107.99.40.127]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20260826052012epsmtip280cd1414e2b0dc05d1c3b4449c8f55c3~PQ1XNA1zy1150111501epsmtip2g; Wed, 26 Aug 2026 05:20:12 +0000 (GMT) From: Shrihari E S To: jic23@kernel.org, junjie.cao@intel.com, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org, qemu-devel@nongnu.org Cc: shrihari.s@samsung.com, arun.george@samsung.com, cpgs@samsung.com, dave@stgolabs.net, dongjoo.seo1@samsung.com, gost.dev@samsung.com, s.neeraj@samsung.com, vikash.k5@samsung.com Subject: [RFC V2 01/10] hw/pci: Refactor flitmode from PCIESlot to PCIEPort. Date: Wed, 26 Aug 2026 11:04:01 +0530 Message-Id: <1437941060.21787732102723.JavaMail.epsvc@epcpadp1new> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260826053410.1322176-1-shrihari.s@samsung.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CMS-MailID: 20260826052014epcas5p11846c6a40fcec4ec4ba441ceb26e5dcc X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P X-CPGSPASS: Y X-Hop-Count: 3 X-CMS-RootMailID: 20260826052014epcas5p11846c6a40fcec4ec4ba441ceb26e5dcc References: <20260826053410.1322176-1-shrihari.s@samsung.com> Move the 'flitmode' property from PCIESlot to PCIEPort. This change allows all the derived ports (PCIe ports or CXL ports) to use this property. This is a structural refactor only. There is no functional change in existing behavior. Note: This property was added from Davidlohr's BI patch series[1]. [1]: https://lore.kernel.org/all/20251103195209.1319917-2-dave@stgolabs.net/ Signed-off-by: Shrihari E S --- hw/pci-bridge/cxl_downstream.c | 6 +++--- hw/pci-bridge/cxl_root_port.c | 6 +++--- hw/pci/pcie.c | 2 +- include/hw/pci/pcie_port.h | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index d1e27994a3..7c7a1d1221 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -118,7 +118,7 @@ static void cxl_dsp_reset(DeviceState *qdev) static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) { - PCIESlot *s = PCIE_SLOT(d); + PCIEPort *p = PCIE_PORT(d); CXLDVSECRegisterLocator *regloc_dvsec; uint8_t *dvsec; int i; @@ -132,7 +132,7 @@ static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){ .cap = 0x27, /* Cache, IO, Mem, non-MLD */ .ctrl = 0x02, /* IO always enabled */ - .status = s->flitmode ? 0x6 : 0x26, /* lack of 68B */ + .status = p->flitmode ? 0x6 : 0x26, /* lack of 68B */ .rcvd_mod_ts_data_phase1 = 0xef, /* WTF? */ }; cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT, @@ -259,7 +259,7 @@ static const Property cxl_dsp_props[] = { speed, PCIE_LINK_SPEED_64), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_16), - DEFINE_PROP_BOOL("x-256b-flit", PCIESlot, flitmode, true), + DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, true), }; static void cxl_dsp_class_init(ObjectClass *oc, const void *data) diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 0ee18ef5c3..df69c5200f 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -112,7 +112,7 @@ static void latch_registers(CXLRootPort *crp) static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) { - PCIESlot *s = PCIE_SLOT(d); + PCIEPort *p = PCIE_PORT(d); CXLDVSECRegisterLocator *regloc_dvsec; uint8_t *dvsec; int i; @@ -135,7 +135,7 @@ static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){ .cap = 0x26, /* IO, Mem, non-MLD */ .ctrl = 0x2, - .status = s->flitmode ? 0x6 : 0x26, /* lack of 68B */ + .status = p->flitmode ? 0x6 : 0x26, /* lack of 68B */ .rcvd_mod_ts_data_phase1 = 0xef, }; cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT, @@ -237,7 +237,7 @@ static const Property gen_rp_props[] = { speed, PCIE_LINK_SPEED_64), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_32), - DEFINE_PROP_BOOL("x-256b-flit", PCIESlot, flitmode, true), + DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, true), }; static void cxl_rp_dvsec_write_config(PCIDevice *dev, uint32_t addr, diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 1de0b1e4fd..4f6fc9db61 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -217,7 +217,7 @@ static void pcie_cap_fill_slot_lnk(PCIDevice *dev) /* the PCI_EXP_LNKSTA_DLLLA will be set in the hotplug function */ } - pcie_cap_fill_lnk(exp_cap, s->width, s->speed, s->flitmode); + pcie_cap_fill_lnk(exp_cap, s->width, s->speed, PCIE_PORT(s)->flitmode); } int pcie_cap_init(PCIDevice *dev, uint8_t offset, diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 53cd64c5ed..1bcc734649 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -33,6 +33,7 @@ struct PCIEPort { /*< private >*/ PCIBridge parent_obj; /*< public >*/ + bool flitmode; /* pci express switch port */ uint8_t port; @@ -58,7 +59,6 @@ struct PCIESlot { PCIExpLinkSpeed speed; PCIExpLinkWidth width; - bool flitmode; /* Disable ACS (really for a pcie_root_port) */ bool disable_acs; -- 2.34.1