From: Yinghai Lu <yinghai@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>,
David Miller <davem@davemloft.net>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Wei Yang <weiyang@linux.vnet.ibm.com>, TJ <linux@iam.tj>,
Yijing Wang <wangyijing@huawei.com>
Cc: Andrew Morton <akpm@linux-foundation.org>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
Yinghai Lu <yinghai@kernel.org>
Subject: [PATCH v4 40/52] sparc/PCI: Add mem64 resource parsing for root bus
Date: Thu, 20 Aug 2015 23:20:55 -0700 [thread overview]
Message-ID: <1440138067-4314-41-git-send-email-yinghai@kernel.org> (raw)
In-Reply-To: <1440138067-4314-1-git-send-email-yinghai@kernel.org>
Found "no compatible bridge window" warning in boot log from T5-8.
pci 0000:00:01.0: can't claim BAR 15 [mem 0x100000000-0x4afffffff pref]: no compatible bridge window
That resource is above 4G, but does not get offset correctly as
root bus only report io and mem32.
pci_sun4v f02dbcfc: PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [io 0x804000000000-0x80400fffffff] (bus address [0x0000-0xfffffff])
pci_bus 0000:00: root bus resource [mem 0x800000000000-0x80007effffff] (bus address [0x00000000-0x7effffff])
pci_bus 0000:00: root bus resource [bus 00-77]
Add mem64 handling in pci_common for sparc, so we can have 64bit resource
registered for root bus at first.
After patch, will have:
pci_sun4v f02dbcfc: PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [io 0x804000000000-0x80400fffffff] (bus address [0x0000-0xfffffff])
pci_bus 0000:00: root bus resource [mem 0x800000000000-0x80007effffff] (bus address [0x00000000-0x7effffff])
pci_bus 0000:00: root bus resource [mem 0x800100000000-0x8007ffffffff] (bus address [0x100000000-0x7ffffffff])
pci_bus 0000:00: root bus resource [bus 00-77]
-v2: mem64_space should use mem_space.start as offset.
-v3: add IORESOURCE_MEM_64 flag
Fixes: commit d63e2e1f3df9 ("sparc/PCI: Clip bridge windows to fit in upstream windows")
Link: http://lkml.kernel.org/r/CAE9FiQU1gJY1LYrxs+ma5LCTEEe4xmtjRG0aXJ9K_Tsu+m9Wuw@mail.gmail.com
Reported-by: David Ahern <david.ahern@oracle.com>
Tested-by: David Ahern <david.ahern@oracle.com>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
arch/sparc/kernel/pci.c | 7 ++++++-
arch/sparc/kernel/pci_common.c | 15 +++++++++++++--
arch/sparc/kernel/pci_impl.h | 1 +
3 files changed, 20 insertions(+), 3 deletions(-)
---
arch/sparc/kernel/pci.c | 7 ++++++-
arch/sparc/kernel/pci_common.c | 15 +++++++++++++--
arch/sparc/kernel/pci_impl.h | 1 +
3 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c
index c928bc6..bfd0b70 100644
--- a/arch/sparc/kernel/pci.c
+++ b/arch/sparc/kernel/pci.c
@@ -185,8 +185,10 @@ static unsigned long pci_parse_of_flags(u32 addr0)
if (addr0 & 0x02000000) {
flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
- flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
+ if (addr0 & 0x01000000)
+ flags |= IORESOURCE_MEM_64
+ | PCI_BASE_ADDRESS_MEM_TYPE_64;
if (addr0 & 0x40000000)
flags |= IORESOURCE_PREFETCH
| PCI_BASE_ADDRESS_MEM_PREFETCH;
@@ -660,6 +662,9 @@ struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
pbm->io_space.start);
pci_add_resource_offset(&resources, &pbm->mem_space,
pbm->mem_space.start);
+ if (pbm->mem64_space.flags)
+ pci_add_resource_offset(&resources, &pbm->mem64_space,
+ pbm->mem_space.start);
pbm->busn.start = pbm->pci_first_busno;
pbm->busn.end = pbm->pci_last_busno;
pbm->busn.flags = IORESOURCE_BUS;
diff --git a/arch/sparc/kernel/pci_common.c b/arch/sparc/kernel/pci_common.c
index 944a065..a859a86 100644
--- a/arch/sparc/kernel/pci_common.c
+++ b/arch/sparc/kernel/pci_common.c
@@ -406,6 +406,7 @@ void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
}
num_pbm_ranges = i / sizeof(*pbm_ranges);
+ memset(&pbm->mem64_space, 0, sizeof(struct resource));
for (i = 0; i < num_pbm_ranges; i++) {
const struct linux_prom_pci_ranges *pr = &pbm_ranges[i];
@@ -451,7 +452,11 @@ void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
break;
case 3:
- /* XXX 64-bit MEM handling XXX */
+ /* 64-bit MEM handling */
+ pbm->mem64_space.start = a;
+ pbm->mem64_space.end = a + size - 1UL;
+ pbm->mem64_space.flags = IORESOURCE_MEM;
+ break;
default:
break;
@@ -465,15 +470,21 @@ void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
prom_halt();
}
- printk("%s: PCI IO[%llx] MEM[%llx]\n",
+ printk("%s: PCI IO[%llx] MEM[%llx]",
pbm->name,
pbm->io_space.start,
pbm->mem_space.start);
+ if (pbm->mem64_space.flags)
+ printk(" MEM64[%llx]",
+ pbm->mem64_space.start);
+ printk("\n");
pbm->io_space.name = pbm->mem_space.name = pbm->name;
request_resource(&ioport_resource, &pbm->io_space);
request_resource(&iomem_resource, &pbm->mem_space);
+ if (pbm->mem64_space.flags)
+ request_resource(&iomem_resource, &pbm->mem64_space);
pci_register_legacy_regions(&pbm->io_space,
&pbm->mem_space);
diff --git a/arch/sparc/kernel/pci_impl.h b/arch/sparc/kernel/pci_impl.h
index 75803c7..37222ca 100644
--- a/arch/sparc/kernel/pci_impl.h
+++ b/arch/sparc/kernel/pci_impl.h
@@ -97,6 +97,7 @@ struct pci_pbm_info {
/* PBM I/O and Memory space resources. */
struct resource io_space;
struct resource mem_space;
+ struct resource mem64_space;
struct resource busn;
/* Base of PCI Config space, can be per-PBM or shared. */
--
1.8.4.5
next prev parent reply other threads:[~2015-08-21 6:22 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-21 6:20 [PATCH v4 00/52] PCI: Resource allocation cleanup for v4.3 Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 01/52] PCI: Cleanup res_to_dev_res() printout Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 02/52] PCI: Reuse res_to_dev_res() in reassign_resources_sorted() Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 03/52] PCI: Use correct align for optional only resources during sorting Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 04/52] PCI: Optimize bus min_align/size calculation during sizing Yinghai Lu
2015-09-14 20:21 ` Bjorn Helgaas
2015-09-14 21:37 ` Yinghai Lu
2015-09-15 14:57 ` Bjorn Helgaas
2015-09-16 19:33 ` Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 05/52] PCI: Optimize bus align/size calculation for optional " Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 06/52] PCI: Don't add too much optional size for hotplug bridge MMIO Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 07/52] PCI: Reorder resources list for required/optional resources Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 08/52] PCI: Remove duplicated code for resource sorting Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 09/52] PCI: Rename pdev_sort_resources() to pdev_assign_resources_prepare() Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 10/52] PCI: Treat ROM resource as optional during realloc Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 11/52] PCI: Add debug printout during releasing partial assigned resources Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 12/52] PCI: Simplify res reference using in __assign_resources_sorted() Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 13/52] PCI, acpiphp: Add missing realloc list checking after resource allocation Yinghai Lu
2015-08-24 22:09 ` Rafael J. Wysocki
2015-08-24 22:14 ` Yinghai Lu
2015-08-25 0:37 ` Rafael J. Wysocki
2015-08-25 0:14 ` Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 14/52] PCI: Add __add_to_list() Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 15/52] PCI: Cache window alignment value during bus sizing Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 16/52] PCI: Check if resource is allocated before trying to assign one Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 17/52] PCI: Separate out save_resources()/restore_resources() Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 18/52] PCI: Move comment to pci_need_to_release() Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 19/52] PCI: Separate required+optional assigning to another function Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 20/52] PCI: Skip required+optional if there is no optional Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 21/52] PCI: Move saved required resource list out of required+optional assigning Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 22/52] PCI: Add alt_size ressource allocation support Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 23/52] PCI: Add support for more than two alt_size under same bridge Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 24/52] PCI: Better support for two alt_size Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 25/52] PCI: Fix size calculation with old_size on rescan path Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 26/52] PCI: Don't add too much optional size for hotplug bridge io Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 27/52] PCI: Move ISA io port align out of calculate_iosize() Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 28/52] PCI: Don't add too much io port for hotplug bridge with old size Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 29/52] PCI: Unify calculate_size() for io port and MMIO Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 30/52] PCI: Allow bridge optional only io port resource required size to be 0 Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 31/52] PCI: Unify skip_ioresource_align() Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 32/52] PCI: Kill macro checking for bus io port sizing Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 33/52] resources: Split out __allocate_resource() Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 34/52] resources: Make allocate_resource() return best fit resource Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 35/52] PCI: Check pref compatible bit for mem64 resource of PCIe device Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 36/52] PCI: Only treat non-pref mmio64 as pref if all bridges have MEM_64 Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 37/52] PCI: Add has_mem64 for struct host_bridge Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 38/52] PCI: Only treat non-pref mmio64 as pref if host bridge has mmio64 Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 39/52] PCI: Restore pref MMIO allocation logic for host bridge without mmio64 Yinghai Lu
2015-08-21 6:20 ` Yinghai Lu [this message]
2015-08-21 6:20 ` [PATCH v4 41/52] sparc/PCI: Add IORESOURCE_MEM_64 for 64-bit resource in OF parsing Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 42/52] powerpc/PCI: " Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 43/52] OF/PCI: Add IORESOURCE_MEM_64 for 64-bit resource Yinghai Lu
2015-08-21 18:18 ` Rob Herring
2015-08-21 18:24 ` Yinghai Lu
2015-08-21 6:20 ` [PATCH v4 44/52] PCI: Treat optional as required in first try for bridge rescan Yinghai Lu
2015-08-21 6:21 ` [PATCH v4 45/52] PCI: Get new realloc size for bridge for last try Yinghai Lu
2015-08-21 6:21 ` [PATCH v4 46/52] PCI: Don't release sibling bridge resources during hotplug Yinghai Lu
2015-08-21 6:21 ` [PATCH v4 47/52] PCI: Don't release fixed resource for realloc Yinghai Lu
2015-08-21 6:21 ` [PATCH v4 48/52] PCI: Claim fixed resource during remove/rescan path Yinghai Lu
2015-08-21 6:21 ` [PATCH v4 49/52] PCI: Set resource to FIXED for LSI devices Yinghai Lu
2015-08-21 6:21 ` [PATCH v4 50/52] PCI, x86: Add pci=assign_pref_bars to reallocate pref BARs Yinghai Lu
2015-08-21 6:21 ` [PATCH v4 51/52] PCI: Introduce resource_disabled() Yinghai Lu
2015-08-21 6:21 ` [PATCH v4 52/52] PCI: Don't set flags to 0 when assign resource fail Yinghai Lu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1440138067-4314-41-git-send-email-yinghai@kernel.org \
--to=yinghai@kernel.org \
--cc=akpm@linux-foundation.org \
--cc=benh@kernel.crashing.org \
--cc=bhelgaas@google.com \
--cc=davem@davemloft.net \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux@iam.tj \
--cc=wangyijing@huawei.com \
--cc=weiyang@linux.vnet.ibm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).