From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mailapp01.imgtec.com ([195.59.15.196]:59036 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965006AbcBDQL3 (ORCPT ); Thu, 4 Feb 2016 11:11:29 -0500 From: Paul Burton To: CC: Bharat Kumar Gogada , Michal Simek , Ravikiran Gummaluri , "Paul Burton" , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , Jiang Liu , "Lorenzo Pieralisi" , Grygorii Strashko , Rob Herring , Bjorn Helgaas , , Russell Joyce , , Thomas Gleixner , Jingoo Han , Subject: [PATCH v3 3/6] PCI: xilinx: Always clear interrupt decode register Date: Thu, 4 Feb 2016 16:10:10 +0000 Message-ID: <1454602213-967-4-git-send-email-paul.burton@imgtec.com> In-Reply-To: <1454602213-967-1-git-send-email-paul.burton@imgtec.com> References: <1454602213-967-1-git-send-email-paul.burton@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-pci-owner@vger.kernel.org List-ID: If an MSI or INTx interrupt is incorrectly triggered with an empty FIFO then xilinx_pcie_intr_handler will print a warning & skip further processing. However it did not clear the interrupt in the decode register, so the same INTX or MSI interrupt would trigger again immediately even though the FIFO is still empty. Clear the interrupt in the decode register to avoid that situation. Signed-off-by: Paul Burton Fixes: 8961def56845 ("PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver") --- Changes in v3: - Split out from Boston patchset. Changes in v2: - Add Fixes tag. drivers/pci/host/pcie-xilinx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index afdfb09..1eb74a2 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -444,7 +444,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) /* Check whether interrupt valid */ if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) { dev_warn(port->dev, "RP Intr FIFO1 read error\n"); - return IRQ_HANDLED; + goto out; } if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { @@ -492,6 +492,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) if (status & XILINX_PCIE_INTR_MST_ERRP) dev_warn(port->dev, "Master error poison\n"); +out: /* Clear the Interrupt Decode register */ pcie_write(port, status, XILINX_PCIE_REG_IDR); -- 2.7.0