From: Jisheng Zhang <jszhang@marvell.com>
To: <jingoohan1@gmail.com>, <pratyush.anand@gmail.com>,
<bhelgaas@google.com>, <Joao.Pinto@synopsys.com>
Cc: Jisheng Zhang <jszhang@marvell.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 1/2] PCI: designware: mv parameters for wait for link into pcie-designware.c
Date: Wed, 10 Aug 2016 18:07:02 +0800 [thread overview]
Message-ID: <1470823623-1360-2-git-send-email-jszhang@marvell.com> (raw)
In-Reply-To: <1470823623-1360-1-git-send-email-jszhang@marvell.com>
These parameters are only used in the core pcie-designware.c, let's
move them to the core driver.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
drivers/pci/host/pcie-designware.c | 5 +++++
drivers/pci/host/pcie-designware.h | 5 -----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 12afce1..24a16dd 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -75,6 +75,11 @@
#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010
+/* Parameters for the waiting for link up routine */
+#define LINK_WAIT_MAX_RETRIES 10
+#define LINK_WAIT_USLEEP_MIN 90000
+#define LINK_WAIT_USLEEP_MAX 100000
+
static struct pci_ops dw_pcie_ops;
int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index f437f9b..384e79b 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -22,11 +22,6 @@
#define MAX_MSI_IRQS 32
#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
-/* Parameters for the waiting for link up routine */
-#define LINK_WAIT_MAX_RETRIES 10
-#define LINK_WAIT_USLEEP_MIN 90000
-#define LINK_WAIT_USLEEP_MAX 100000
-
struct pcie_port {
struct device *dev;
u8 root_bus_nr;
--
2.8.1
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next prev parent reply other threads:[~2016-08-10 10:07 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-10 10:07 [PATCH v2 0/2] PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit Jisheng Zhang
2016-08-10 10:07 ` Jisheng Zhang [this message]
2016-08-10 10:07 ` [PATCH v2 2/2] " Jisheng Zhang
2016-08-10 10:21 ` [PATCH v2 0/2] " Jisheng Zhang
2016-08-17 21:01 ` Bjorn Helgaas
-- strict thread matches above, loose matches on Subject: below --
2016-08-10 5:31 Jisheng Zhang
2016-08-10 5:31 ` [PATCH v2 1/2] PCI: designware: mv parameters for wait for link into pcie-designware.c Jisheng Zhang
2016-08-14 16:01 ` Pratyush Anand
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