* [PATCH] lspci: Parse all the L1 PM substate capability regs
@ 2016-09-01 16:27 Rajat Jain
2016-09-09 0:05 ` [PATCH v2] " Rajat Jain
0 siblings, 1 reply; 9+ messages in thread
From: Rajat Jain @ 2016-09-01 16:27 UTC (permalink / raw)
To: Martin Mares, bhelgaas, linux-pci, David Box
Cc: Rajat Jain, rajatxjain, briannorris
Parse the control registers to display all the L1 PM
substate configuration information.
Signed-off-by: Rajat Jain <rajatja@google.com>
---
I tested it on my Rockchip hardware that shows it correctly.
I couldn't figure out how to "test" the tests (is there a
documentation / example on running tests?), and hence left
tests/cap-l1-pm unchanged.
| 14 +++++++++
ls-ecaps.c | 92 ++++++++++++++++++++++++++++++++++++++++++------------------
2 files changed, 78 insertions(+), 28 deletions(-)
--git a/lib/header.h b/lib/header.h
index 1c5968b..0341ec6 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -1117,6 +1117,20 @@
#define PCI_DPC_STS_PIO_FEP(x) (((x) >> 8) & 0x1f) /* DPC PIO First Error Pointer */
#define PCI_DPC_SOURCE 10 /* DPC Source ID */
+/* L1 PM Substates Extended Capability */
+#define PCI_L1PM_SUBSTAT_CAP 0x4 /* L1 PM Substate Capability */
+#define PCI_L1PM_SUBSTAT_CAP_PM_L12 0x1 /* PCI-PM L1.2 Supported */
+#define PCI_L1PM_SUBSTAT_CAP_PM_L11 0x2 /* PCI-PM L1.1 Supported */
+#define PCI_L1PM_SUBSTAT_CAP_ASPM_L12 0x4 /* ASPM L1.2 Supported */
+#define PCI_L1PM_SUBSTAT_CAP_ASPM_L11 0x8 /* ASPM L1.1 Supported */
+#define PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP 0x16 /* L1 Pm Substates supported */
+#define PCI_L1PM_SUBSTAT_CTL1 0x8 /* L1 PM Substate Control 1 */
+#define PCI_L1PM_SUBSTAT_CTL1_PM_L12 0x1 /* PCI-PM L1.2 Enable */
+#define PCI_L1PM_SUBSTAT_CTL1_PM_L11 0x2 /* PCI-PM L1.1 Enable */
+#define PCI_L1PM_SUBSTAT_CTL1_ASPM_L12 0x4 /* ASPM L1.2 Enable */
+#define PCI_L1PM_SUBSTAT_CTL1_ASPM_L11 0x8 /* ASPM L1.1 Enable */
+#define PCI_L1PM_SUBSTAT_CTL2 0xC /* L1 PM Substate Control 2 */
+
/*
* The PCI interface treats multi-function devices as independent
* devices. The slot/function address of each device is encoded
diff --git a/ls-ecaps.c b/ls-ecaps.c
index 5e18e06..7705930 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -527,55 +527,91 @@ cap_evendor(struct device *d, int where)
BITS(hdr, 20, 12));
}
+static inline int l1pm_scale_value(int scale, int value)
+{
+ switch (scale)
+ {
+ case 0:
+ return 2 * value;
+ case 1:
+ return 10 * value;
+ case 2:
+ return 100 * value;
+ }
+ return -1;
+}
+
static void
cap_l1pm(struct device *d, int where)
{
- u32 l1_cap;
- int power_on_scale;
+ u32 l1_cap, val;
+ int time;
printf("L1 PM Substates\n");
if (verbose < 2)
return;
- if (!config_fetch(d, where + 4, 4))
+ if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12))
{
printf("\t\t<unreadable>\n");
return;
}
- l1_cap = get_conf_long(d, where + 4);
+ l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP);
printf("\t\tL1SubCap: ");
printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
- FLAG(l1_cap, 1),
- FLAG(l1_cap, 2),
- FLAG(l1_cap, 4),
- FLAG(l1_cap, 8),
- FLAG(l1_cap, 16));
-
- if (BITS(l1_cap, 0, 1) || BITS(l1_cap, 2, 1))
+ FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12),
+ FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11),
+ FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12),
+ FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11),
+ FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP));
+
+ if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 ||
+ l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
{
printf("\t\t\t PortCommonModeRestoreTime=%dus ",
BITS(l1_cap, 8,8));
- power_on_scale = BITS(l1_cap, 16, 2);
+ time = l1pm_scale_value(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5));
+ if (time != -1)
+ printf("PortTPowerOnTime=%dus\n", time);
+ else
+ printf("PortTPowerOnTime=<error>\n");
+ }
- printf("PortTPowerOnTime=");
- switch (power_on_scale)
- {
- case 0:
- printf("%dus\n", BITS(l1_cap, 19, 5) * 2);
- break;
- case 1:
- printf("%dus\n", BITS(l1_cap, 19, 5) * 10);
- break;
- case 2:
- printf("%dus\n", BITS(l1_cap, 19, 5) * 100);
- break;
- default:
- printf("<error>\n");
- break;
- }
+ val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1);
+ printf("\t\tL1SubCtl1: ");
+ printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n",
+ FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12),
+ FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11),
+ FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12),
+ FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11));
+
+ if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 ||
+ l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
+ printf("\t\t\t T_CommonMode=%dus ",
+ BITS(val, 8,8));
+
+ if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
+ {
+ time = l1pm_scale_value(BITS(val, 29, 3), BITS(val, 16, 10));
+ if (time != -1)
+ printf("LTR1.2_Threshhold=%dus\n", time);
+ else
+ printf("LTR1.2_Threshhold=<error>\n");
+ }
+
+ val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2);
+ printf("\t\tL1SubCtl2: ");
+ if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 ||
+ l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
+ {
+ time = l1pm_scale_value(BITS(val, 0, 2), BITS(val, 3, 5));
+ if (time != -1)
+ printf("T_PwrOn=%dus\n", time);
+ else
+ printf("T_PwrOn=<error>\n");
}
}
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2] lspci: Parse all the L1 PM substate capability regs
2016-09-01 16:27 [PATCH] lspci: Parse all the L1 PM substate capability regs Rajat Jain
@ 2016-09-09 0:05 ` Rajat Jain
2016-09-22 21:40 ` Rajat Jain
0 siblings, 1 reply; 9+ messages in thread
From: Rajat Jain @ 2016-09-09 0:05 UTC (permalink / raw)
To: Martin Mares, bhelgaas, linux-pci, David Box
Cc: Rajat Jain, rajatxjain, briannorris
Parse the control registers to display all the L1 PM
substate configuration information.
Signed-off-by: Rajat Jain <rajatja@google.com>
---
V2: Fix the LTR1.2 threshold scaling
| 14 +++++++++
ls-ecaps.c | 94 ++++++++++++++++++++++++++++++++++++++++++------------------
2 files changed, 80 insertions(+), 28 deletions(-)
--git a/lib/header.h b/lib/header.h
index 1c5968b..0341ec6 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -1117,6 +1117,20 @@
#define PCI_DPC_STS_PIO_FEP(x) (((x) >> 8) & 0x1f) /* DPC PIO First Error Pointer */
#define PCI_DPC_SOURCE 10 /* DPC Source ID */
+/* L1 PM Substates Extended Capability */
+#define PCI_L1PM_SUBSTAT_CAP 0x4 /* L1 PM Substate Capability */
+#define PCI_L1PM_SUBSTAT_CAP_PM_L12 0x1 /* PCI-PM L1.2 Supported */
+#define PCI_L1PM_SUBSTAT_CAP_PM_L11 0x2 /* PCI-PM L1.1 Supported */
+#define PCI_L1PM_SUBSTAT_CAP_ASPM_L12 0x4 /* ASPM L1.2 Supported */
+#define PCI_L1PM_SUBSTAT_CAP_ASPM_L11 0x8 /* ASPM L1.1 Supported */
+#define PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP 0x16 /* L1 Pm Substates supported */
+#define PCI_L1PM_SUBSTAT_CTL1 0x8 /* L1 PM Substate Control 1 */
+#define PCI_L1PM_SUBSTAT_CTL1_PM_L12 0x1 /* PCI-PM L1.2 Enable */
+#define PCI_L1PM_SUBSTAT_CTL1_PM_L11 0x2 /* PCI-PM L1.1 Enable */
+#define PCI_L1PM_SUBSTAT_CTL1_ASPM_L12 0x4 /* ASPM L1.2 Enable */
+#define PCI_L1PM_SUBSTAT_CTL1_ASPM_L11 0x8 /* ASPM L1.1 Enable */
+#define PCI_L1PM_SUBSTAT_CTL2 0xC /* L1 PM Substate Control 2 */
+
/*
* The PCI interface treats multi-function devices as independent
* devices. The slot/function address of each device is encoded
diff --git a/ls-ecaps.c b/ls-ecaps.c
index 5e18e06..40f8cb9 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -527,55 +527,93 @@ cap_evendor(struct device *d, int where)
BITS(hdr, 20, 12));
}
+static inline int l1pm_calc_pwron(int scale, int value)
+{
+ switch (scale)
+ {
+ case 0:
+ return 2 * value;
+ case 1:
+ return 10 * value;
+ case 2:
+ return 100 * value;
+ }
+ return -1;
+}
+
static void
cap_l1pm(struct device *d, int where)
{
- u32 l1_cap;
- int power_on_scale;
+ u32 l1_cap, val, scale;
+ int time;
printf("L1 PM Substates\n");
if (verbose < 2)
return;
- if (!config_fetch(d, where + 4, 4))
+ if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12))
{
printf("\t\t<unreadable>\n");
return;
}
- l1_cap = get_conf_long(d, where + 4);
+ l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP);
printf("\t\tL1SubCap: ");
printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
- FLAG(l1_cap, 1),
- FLAG(l1_cap, 2),
- FLAG(l1_cap, 4),
- FLAG(l1_cap, 8),
- FLAG(l1_cap, 16));
-
- if (BITS(l1_cap, 0, 1) || BITS(l1_cap, 2, 1))
+ FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12),
+ FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11),
+ FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12),
+ FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11),
+ FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP));
+
+ if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 ||
+ l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
{
printf("\t\t\t PortCommonModeRestoreTime=%dus ",
BITS(l1_cap, 8,8));
- power_on_scale = BITS(l1_cap, 16, 2);
+ time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5));
+ if (time != -1)
+ printf("PortTPowerOnTime=%dus\n", time);
+ else
+ printf("PortTPowerOnTime=<error>\n");
+ }
- printf("PortTPowerOnTime=");
- switch (power_on_scale)
- {
- case 0:
- printf("%dus\n", BITS(l1_cap, 19, 5) * 2);
- break;
- case 1:
- printf("%dus\n", BITS(l1_cap, 19, 5) * 10);
- break;
- case 2:
- printf("%dus\n", BITS(l1_cap, 19, 5) * 100);
- break;
- default:
- printf("<error>\n");
- break;
- }
+ val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1);
+ printf("\t\tL1SubCtl1: ");
+ printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n",
+ FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12),
+ FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11),
+ FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12),
+ FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11));
+
+ if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 ||
+ l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
+ printf("\t\t\t T_CommonMode=%dus ",
+ BITS(val, 8,8));
+
+ if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
+ {
+ scale = BITS(val, 29, 3);
+ if (scale > 5)
+ printf("LTR1.2_Threshhold=<error>\n");
+ else
+ printf("LTR1.2_Threshhold=%lldns\n",
+ BITS(val, 16, 10) *
+ (unsigned long long)cap_ltr_scale(scale));
+ }
+
+ val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2);
+ printf("\t\tL1SubCtl2: ");
+ if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 ||
+ l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
+ {
+ time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5));
+ if (time != -1)
+ printf("T_PwrOn=%dus\n", time);
+ else
+ printf("T_PwrOn=<error>\n");
}
}
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2] lspci: Parse all the L1 PM substate capability regs
2016-09-09 0:05 ` [PATCH v2] " Rajat Jain
@ 2016-09-22 21:40 ` Rajat Jain
2016-09-26 18:23 ` Martin Mares
0 siblings, 1 reply; 9+ messages in thread
From: Rajat Jain @ 2016-09-22 21:40 UTC (permalink / raw)
To: Martin Mares, Bjorn Helgaas, linux-pci, David Box
Cc: Rajat Jain, Rajat Jain, Brian Norris
Hello Matrin,
Just checking if you got a chance to look at this.
Thanks,
Rajat
On Thu, Sep 8, 2016 at 5:05 PM, Rajat Jain <rajatja@google.com> wrote:
> Parse the control registers to display all the L1 PM
> substate configuration information.
>
> Signed-off-by: Rajat Jain <rajatja@google.com>
> ---
> V2: Fix the LTR1.2 threshold scaling
>
> lib/header.h | 14 +++++++++
> ls-ecaps.c | 94 ++++++++++++++++++++++++++++++++++++++++++------------------
> 2 files changed, 80 insertions(+), 28 deletions(-)
>
> diff --git a/lib/header.h b/lib/header.h
> index 1c5968b..0341ec6 100644
> --- a/lib/header.h
> +++ b/lib/header.h
> @@ -1117,6 +1117,20 @@
> #define PCI_DPC_STS_PIO_FEP(x) (((x) >> 8) & 0x1f) /* DPC PIO First Error Pointer */
> #define PCI_DPC_SOURCE 10 /* DPC Source ID */
>
> +/* L1 PM Substates Extended Capability */
> +#define PCI_L1PM_SUBSTAT_CAP 0x4 /* L1 PM Substate Capability */
> +#define PCI_L1PM_SUBSTAT_CAP_PM_L12 0x1 /* PCI-PM L1.2 Supported */
> +#define PCI_L1PM_SUBSTAT_CAP_PM_L11 0x2 /* PCI-PM L1.1 Supported */
> +#define PCI_L1PM_SUBSTAT_CAP_ASPM_L12 0x4 /* ASPM L1.2 Supported */
> +#define PCI_L1PM_SUBSTAT_CAP_ASPM_L11 0x8 /* ASPM L1.1 Supported */
> +#define PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP 0x16 /* L1 Pm Substates supported */
> +#define PCI_L1PM_SUBSTAT_CTL1 0x8 /* L1 PM Substate Control 1 */
> +#define PCI_L1PM_SUBSTAT_CTL1_PM_L12 0x1 /* PCI-PM L1.2 Enable */
> +#define PCI_L1PM_SUBSTAT_CTL1_PM_L11 0x2 /* PCI-PM L1.1 Enable */
> +#define PCI_L1PM_SUBSTAT_CTL1_ASPM_L12 0x4 /* ASPM L1.2 Enable */
> +#define PCI_L1PM_SUBSTAT_CTL1_ASPM_L11 0x8 /* ASPM L1.1 Enable */
> +#define PCI_L1PM_SUBSTAT_CTL2 0xC /* L1 PM Substate Control 2 */
> +
> /*
> * The PCI interface treats multi-function devices as independent
> * devices. The slot/function address of each device is encoded
> diff --git a/ls-ecaps.c b/ls-ecaps.c
> index 5e18e06..40f8cb9 100644
> --- a/ls-ecaps.c
> +++ b/ls-ecaps.c
> @@ -527,55 +527,93 @@ cap_evendor(struct device *d, int where)
> BITS(hdr, 20, 12));
> }
>
> +static inline int l1pm_calc_pwron(int scale, int value)
> +{
> + switch (scale)
> + {
> + case 0:
> + return 2 * value;
> + case 1:
> + return 10 * value;
> + case 2:
> + return 100 * value;
> + }
> + return -1;
> +}
> +
> static void
> cap_l1pm(struct device *d, int where)
> {
> - u32 l1_cap;
> - int power_on_scale;
> + u32 l1_cap, val, scale;
> + int time;
>
> printf("L1 PM Substates\n");
>
> if (verbose < 2)
> return;
>
> - if (!config_fetch(d, where + 4, 4))
> + if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12))
> {
> printf("\t\t<unreadable>\n");
> return;
> }
>
> - l1_cap = get_conf_long(d, where + 4);
> + l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP);
> printf("\t\tL1SubCap: ");
> printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
> - FLAG(l1_cap, 1),
> - FLAG(l1_cap, 2),
> - FLAG(l1_cap, 4),
> - FLAG(l1_cap, 8),
> - FLAG(l1_cap, 16));
> -
> - if (BITS(l1_cap, 0, 1) || BITS(l1_cap, 2, 1))
> + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12),
> + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11),
> + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12),
> + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11),
> + FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP));
> +
> + if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 ||
> + l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
> {
> printf("\t\t\t PortCommonModeRestoreTime=%dus ",
> BITS(l1_cap, 8,8));
>
> - power_on_scale = BITS(l1_cap, 16, 2);
> + time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5));
> + if (time != -1)
> + printf("PortTPowerOnTime=%dus\n", time);
> + else
> + printf("PortTPowerOnTime=<error>\n");
> + }
>
> - printf("PortTPowerOnTime=");
> - switch (power_on_scale)
> - {
> - case 0:
> - printf("%dus\n", BITS(l1_cap, 19, 5) * 2);
> - break;
> - case 1:
> - printf("%dus\n", BITS(l1_cap, 19, 5) * 10);
> - break;
> - case 2:
> - printf("%dus\n", BITS(l1_cap, 19, 5) * 100);
> - break;
> - default:
> - printf("<error>\n");
> - break;
> - }
> + val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1);
> + printf("\t\tL1SubCtl1: ");
> + printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n",
> + FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12),
> + FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11),
> + FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12),
> + FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11));
> +
> + if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 ||
> + l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
> + printf("\t\t\t T_CommonMode=%dus ",
> + BITS(val, 8,8));
> +
> + if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
> + {
> + scale = BITS(val, 29, 3);
> + if (scale > 5)
> + printf("LTR1.2_Threshhold=<error>\n");
> + else
> + printf("LTR1.2_Threshhold=%lldns\n",
> + BITS(val, 16, 10) *
> + (unsigned long long)cap_ltr_scale(scale));
> + }
> +
> + val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2);
> + printf("\t\tL1SubCtl2: ");
> + if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 ||
> + l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
> + {
> + time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5));
> + if (time != -1)
> + printf("T_PwrOn=%dus\n", time);
> + else
> + printf("T_PwrOn=<error>\n");
> }
> }
>
> --
> 2.8.0.rc3.226.g39d4020
>
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v2] lspci: Parse all the L1 PM substate capability regs
2016-09-22 21:40 ` Rajat Jain
@ 2016-09-26 18:23 ` Martin Mares
2016-09-26 18:26 ` Rajat Jain
0 siblings, 1 reply; 9+ messages in thread
From: Martin Mares @ 2016-09-26 18:23 UTC (permalink / raw)
To: Rajat Jain; +Cc: Bjorn Helgaas, linux-pci, David Box, Rajat Jain, Brian Norris
Hello!
> Just checking if you got a chance to look at this.
It currently lives in the l1pm branch of pciutils.git, together with
a couple of my cleanups. Most importantly, your original patch did sometimes
print unterminated lines.
Could you please check my version and submit a test case (a hex dump of
a config space with this capability, like those in tests/*).
Martin
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] lspci: Parse all the L1 PM substate capability regs
2016-09-26 18:23 ` Martin Mares
@ 2016-09-26 18:26 ` Rajat Jain
2016-09-26 18:27 ` Rajat Jain
0 siblings, 1 reply; 9+ messages in thread
From: Rajat Jain @ 2016-09-26 18:26 UTC (permalink / raw)
To: Martin Mares
Cc: Bjorn Helgaas, linux-pci, David Box, Rajat Jain, Brian Norris
Will do, thanks!
On Mon, Sep 26, 2016 at 11:23 AM, Martin Mares <mj@ucw.cz> wrote:
> Hello!
>
>> Just checking if you got a chance to look at this.
>
> It currently lives in the l1pm branch of pciutils.git, together with
> a couple of my cleanups. Most importantly, your original patch did sometimes
> print unterminated lines.
>
> Could you please check my version and submit a test case (a hex dump of
> a config space with this capability, like those in tests/*).
>
> Martin
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] lspci: Parse all the L1 PM substate capability regs
2016-09-26 18:26 ` Rajat Jain
@ 2016-09-26 18:27 ` Rajat Jain
2016-09-26 18:28 ` Martin Mares
0 siblings, 1 reply; 9+ messages in thread
From: Rajat Jain @ 2016-09-26 18:27 UTC (permalink / raw)
To: Martin Mares
Cc: Bjorn Helgaas, linux-pci, David Box, Rajat Jain, Brian Norris
On Mon, Sep 26, 2016 at 11:26 AM, Rajat Jain <rajatja@google.com> wrote:
> Will do, thanks!
>
> On Mon, Sep 26, 2016 at 11:23 AM, Martin Mares <mj@ucw.cz> wrote:
>> Hello!
>>
>>> Just checking if you got a chance to look at this.
>>
>> It currently lives in the l1pm branch of pciutils.git, together with
>> a couple of my cleanups. Most importantly, your original patch did sometimes
>> print unterminated lines.
>>
>> Could you please check my version and submit a test case (a hex dump of
>> a config space with this capability, like those in tests/*).
I'll send the hex dump, however I do not know how to actually run the
test. I assume it is fine to just send a patch to tests/ that has the
hex dump.
>>
>> Martin
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] lspci: Parse all the L1 PM substate capability regs
2016-09-26 18:27 ` Rajat Jain
@ 2016-09-26 18:28 ` Martin Mares
2016-10-01 0:43 ` Rajat Jain
0 siblings, 1 reply; 9+ messages in thread
From: Martin Mares @ 2016-09-26 18:28 UTC (permalink / raw)
To: Rajat Jain; +Cc: Bjorn Helgaas, linux-pci, David Box, Rajat Jain, Brian Norris
Hi!
> I'll send the hex dump, however I do not know how to actually run the
> test. I assume it is fine to just send a patch to tests/ that has the
> hex dump.
Exactly.
So far, the tests are conducted manually.
Have a nice fortnight
--
Martin `MJ' Mares <mj@ucw.cz> http://mj.ucw.cz/
Faculty of Math and Physics, Charles University, Prague, Czech Rep., Earth
System going down at 5 pm to install scheduler bug.
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] lspci: Parse all the L1 PM substate capability regs
2016-09-26 18:28 ` Martin Mares
@ 2016-10-01 0:43 ` Rajat Jain
2016-10-03 19:50 ` Martin Mares
0 siblings, 1 reply; 9+ messages in thread
From: Rajat Jain @ 2016-10-01 0:43 UTC (permalink / raw)
To: Martin Mares
Cc: Bjorn Helgaas, linux-pci, David Box, Rajat Jain, Brian Norris
Hi Martin,
Sorry, it took me a while to respond. I've just sent out a patch for
tests/cap-l1-pm that has the data for tests.
Yes, your new patch worked fine.
Thanks,
Rajat
On Mon, Sep 26, 2016 at 11:28 AM, Martin Mares <mj@ucw.cz> wrote:
> Hi!
>
>> I'll send the hex dump, however I do not know how to actually run the
>> test. I assume it is fine to just send a patch to tests/ that has the
>> hex dump.
>
> Exactly.
>
> So far, the tests are conducted manually.
>
> Have a nice fortnight
> --
> Martin `MJ' Mares <mj@ucw.cz> http://mj.ucw.cz/
> Faculty of Math and Physics, Charles University, Prague, Czech Rep., Earth
> System going down at 5 pm to install scheduler bug.
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2016-10-03 19:50 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-09-01 16:27 [PATCH] lspci: Parse all the L1 PM substate capability regs Rajat Jain
2016-09-09 0:05 ` [PATCH v2] " Rajat Jain
2016-09-22 21:40 ` Rajat Jain
2016-09-26 18:23 ` Martin Mares
2016-09-26 18:26 ` Rajat Jain
2016-09-26 18:27 ` Rajat Jain
2016-09-26 18:28 ` Martin Mares
2016-10-01 0:43 ` Rajat Jain
2016-10-03 19:50 ` Martin Mares
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