[PATCH 1/3] PCI: imx6: Improve binding example

[PATCH 1/3] PCI: imx6: Improve binding example

[Fabio Estevam]

Make the binding example to match what is really used in imx6qdl.dtsi.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
 .../devicetree/bindings/pci/fsl,imx6q-pcie.txt        | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index 83aeb1f..1cc8b74 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
@@ -36,7 +36,7 @@ Additional required properties for imx6sx-pcie:
 
 Example:
 
-	pcie@0x01000000 {
+	pcie: pcie@0x01000000 {
 		compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 		reg = <0x01ffc000 0x04000>,
 		      <0x01f00000 0x80000>;
@@ -44,18 +44,19 @@ Example:
 		#address-cells = <3>;
 		#size-cells = <2>;
 		device_type = "pci";
-		ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000
-			  0x81000000 0 0          0x01f80000 0 0x00010000
-			  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
+		ranges = <0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
+			  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 		num-lanes = <1>;
 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "msi";
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 0 0x7>;
-		interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
-		                <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
-		                <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-		                <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clks 144>, <&clks 206>, <&clks 189>;
+		interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
+			 <&clks IMX6QDL_CLK_LVDS1_GATE>,
+			 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
 		clock-names = "pcie", "pcie_bus", "pcie_phy";
 	};
-- 
2.7.4

[PATCH 2/3] MAINTAINERS: PCI: imx6: Use Richard Zhu's NXP email

[Fabio Estevam]

FSL emails may become invalid soon, so switch to the NXP one.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 8544cd6..cf828f4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9257,7 +9257,7 @@ S:	Maintained
 F:	drivers/pci/host/*layerscape*
 
 PCI DRIVER FOR IMX6
-M:	Richard Zhu <Richard.Zhu@freescale.com>
+M:	Richard Zhu <hongxing.zhu@nxp.com>
 M:	Lucas Stach <l.stach@pengutronix.de>
 L:	linux-pci@vger.kernel.org
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-- 
2.7.4

Re: [PATCH 2/3] MAINTAINERS: PCI: imx6: Use Richard Zhu's NXP email

[Fabio Estevam]

Hi Richard,

On Wed, Oct 26, 2016 at 2:27 PM, Fabio Estevam <fabio.estevam@nxp.com> wrote:
> FSL emails may become invalid soon, so switch to the NXP one.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

Are you OK with this patch? If so, please send your Acked-by.

RE: [PATCH 2/3] MAINTAINERS: PCI: imx6: Use Richard Zhu's NXP email

[Richard Zhu]

PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBGYWJpbyBFc3RldmFtIFttYWls
dG86ZmVzdGV2YW1AZ21haWwuY29tXQ0KPiBTZW50OiBNb25kYXksIE5vdmVtYmVyIDA3LCAyMDE2
IDExOjQxIFBNDQo+IFRvOiBSaWNoYXJkIFpodSA8aG9uZ3hpbmcuemh1QG54cC5jb20+DQo+IENj
OiBCam9ybiBIZWxnYWFzIDxiaGVsZ2Fhc0Bnb29nbGUuY29tPjsgTHVjYXMgU3RhY2gNCj4gPGwu
c3RhY2hAcGVuZ3V0cm9uaXguZGU+OyBGYWJpbyBFc3RldmFtIDxmYWJpby5lc3RldmFtQG54cC5j
b20+OyBsaW51eC0NCj4gcGNpQHZnZXIua2VybmVsLm9yZw0KPiBTdWJqZWN0OiBSZTogW1BBVENI
IDIvM10gTUFJTlRBSU5FUlM6IFBDSTogaW14NjogVXNlIFJpY2hhcmQgWmh1J3MgTlhQDQo+IGVt
YWlsDQo+IA0KPiBIaSBSaWNoYXJkLA0KPiANCj4gT24gV2VkLCBPY3QgMjYsIDIwMTYgYXQgMjoy
NyBQTSwgRmFiaW8gRXN0ZXZhbSA8ZmFiaW8uZXN0ZXZhbUBueHAuY29tPg0KPiB3cm90ZToNCj4g
PiBGU0wgZW1haWxzIG1heSBiZWNvbWUgaW52YWxpZCBzb29uLCBzbyBzd2l0Y2ggdG8gdGhlIE5Y
UCBvbmUuDQo+ID4NCj4gPiBTaWduZWQtb2ZmLWJ5OiBGYWJpbyBFc3RldmFtIDxmYWJpby5lc3Rl
dmFtQG54cC5jb20+DQo+IA0KPiBBcmUgeW91IE9LIHdpdGggdGhpcyBwYXRjaD8gSWYgc28sIHBs
ZWFzZSBzZW5kIHlvdXIgQWNrZWQtYnkuDQpIaSBGYWJpbzoNCkknbSBva2F5IHdpdGggaXQuIFRo
YW5rcy4NCg0KQWNrZWQtYnk6IFJpY2hhcmQgWmh1IDxob25neGluZy56aHVAbnhwLmNvbT4NCg0K
QmVzdCBSZWdhcmRzDQpob25neGluZyB6aHUNCkxpbnV4IEJTUCB0ZWFtDQpPZmZpY2U6IDg2LTIx
LTI4OTM3MTg5DQpFbWFpbDogaG9uZ3hpbmcuemh1QG54cC5jb20NCg==

Re: [PATCH 2/3] MAINTAINERS: PCI: imx6: Use Richard Zhu's NXP email

[Bjorn Helgaas]

On Wed, Oct 26, 2016 at 02:27:23PM -0200, Fabio Estevam wrote:
> FSL emails may become invalid soon, so switch to the NXP one.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

I applied patches 2 & 3 (MAINTAINERS updates) with acks from Richard and
Lucas.  I put these on for-linus, so they should go in v4.9 if I have any
more stuff to send to Linus before then.  I probably won't ask him to pull
*just* these, so if by some chance I don't have any more v4.9 material,
they will appear in v4.10.

> ---
>  MAINTAINERS | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8544cd6..cf828f4 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -9257,7 +9257,7 @@ S:	Maintained
>  F:	drivers/pci/host/*layerscape*
>  
>  PCI DRIVER FOR IMX6
> -M:	Richard Zhu <Richard.Zhu@freescale.com>
> +M:	Richard Zhu <hongxing.zhu@nxp.com>
>  M:	Lucas Stach <l.stach@pengutronix.de>
>  L:	linux-pci@vger.kernel.org
>  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> -- 
> 2.7.4
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 2/3] MAINTAINERS: PCI: imx6: Use Richard Zhu's NXP email

[Fabio Estevam]

Hi Bjorn,

On Fri, Nov 11, 2016 at 8:54 PM, Bjorn Helgaas <helgaas@kernel.org> wrote:

> I applied patches 2 & 3 (MAINTAINERS updates) with acks from Richard and
> Lucas.  I put these on for-linus, so they should go in v4.9 if I have any
> more stuff to send to Linus before then.  I probably won't ask him to pull
> *just* these, so if by some chance I don't have any more v4.9 material,
> they will appear in v4.10.

Sounds good, thanks.

[PATCH 3/3] MAINTAINERS: PCI: imx6: Add devicetree binding file

[Fabio Estevam]

Add an entry for the devicetree binding file, so that when
people run ./scripts/get_maintainer.pl the PCI imx6 maintainers could
also be listed.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index cf828f4..d61aead 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9262,6 +9262,7 @@ M:	Lucas Stach <l.stach@pengutronix.de>
 L:	linux-pci@vger.kernel.org
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
+F:	Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
 F:	drivers/pci/host/*imx6*
 
 PCI DRIVER FOR TI KEYSTONE
-- 
2.7.4

Re: [PATCH 3/3] MAINTAINERS: PCI: imx6: Add devicetree binding file

[Lucas Stach]

Am Mittwoch, den 26.10.2016, 14:27 -0200 schrieb Fabio Estevam:
> Add an entry for the devicetree binding file, so that when
> people run ./scripts/get_maintainer.pl the PCI imx6 maintainers could
> also be listed.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

Acked-by: Lucas Stach <l.stach@pengutronix.de>

> ---
>  MAINTAINERS | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index cf828f4..d61aead 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -9262,6 +9262,7 @@ M:	Lucas Stach <l.stach@pengutronix.de>
>  L:	linux-pci@vger.kernel.org
>  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
>  S:	Maintained
> +F:	Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
>  F:	drivers/pci/host/*imx6*
>  
>  PCI DRIVER FOR TI KEYSTONE

Re: [PATCH 1/3] PCI: imx6: Improve binding example

[Lucas Stach]

Am Mittwoch, den 26.10.2016, 14:27 -0200 schrieb Fabio Estevam:
> Make the binding example to match what is really used in imx6qdl.dtsi.
> 
This seems like needless churn to me. After all this is an example and a
valid one, even if some of the references have changed. The fields
itself are in line with the documentation above.

> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
> ---
>  .../devicetree/bindings/pci/fsl,imx6q-pcie.txt        | 19 ++++++++++---------
>  1 file changed, 10 insertions(+), 9 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> index 83aeb1f..1cc8b74 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> @@ -36,7 +36,7 @@ Additional required properties for imx6sx-pcie:
>  
>  Example:
>  
> -	pcie@0x01000000 {
> +	pcie: pcie@0x01000000 {
>  		compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
>  		reg = <0x01ffc000 0x04000>,
>  		      <0x01f00000 0x80000>;
> @@ -44,18 +44,19 @@ Example:
>  		#address-cells = <3>;
>  		#size-cells = <2>;
>  		device_type = "pci";
> -		ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000
> -			  0x81000000 0 0          0x01f80000 0 0x00010000
> -			  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
> +		ranges = <0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
> +			  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
>  		num-lanes = <1>;
>  		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
>  		interrupt-names = "msi";
>  		#interrupt-cells = <1>;
>  		interrupt-map-mask = <0 0 0 0x7>;
> -		interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> -		                <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
> -		                <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
> -		                <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> -		clocks = <&clks 144>, <&clks 206>, <&clks 189>;
> +		interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> +				<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
> +				<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
> +				<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
> +			 <&clks IMX6QDL_CLK_LVDS1_GATE>,
> +			 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
>  		clock-names = "pcie", "pcie_bus", "pcie_phy";
>  	};