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From: Rajat Jain <rajatja@google.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Keith Busch <keith.busch@intel.com>,
	Andreas Ziegler <andreas.ziegler@fau.de>,
	Jonathan Yong <jonathan.yong@intel.com>,
	Shawn Lin <shawn.lin@rock-chips.com>,
	David Daney <david.daney@cavium.com>,
	Julia Lawall <Julia.Lawall@lip6.fr>,
	Ram Amrani <Ram.Amrani@cavium.com>,
	Doug Ledford <dledford@redhat.com>,
	Wang Sheng-Hui <shhuiw@foxmail.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Rajat Jain <rajatja@google.com>,
	Rajat Jain <rajatxjain@gmail.com>,
	Brian Norris <briannorris@google.com>
Subject: [PATCH 0/6] PCI/ASPM: Add PCIe L1 PM substate support
Date: Mon,  2 Jan 2017 22:34:09 -0800	[thread overview]
Message-ID: <1483425255-101923-1-git-send-email-rajatja@google.com> (raw)

This patchset adds the PCIe L1 PM substate support to the kernel.
The feature is described at:
https://pcisig.com/sites/default/files/specification_documents/ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf

Its all logically one patch (and may be some of them should be
squashed later) , but I've broken down into smaller patches for
ease of review. 

This is currently rebased on top of Bjorn's master branch.

Rajat Jain (6):
  PCI: Add L1 substate capability structure register definitions
  PCI/ASPM: Introduce L1 substates and a Kconfig for it
  PCI/ASPM: Read and setup L1 substate capabilities
  PCI/ASPM: Calculate and save the L1.2 timing parameters
  PCI/ASPM: Actually configure the L1 substate settings to the device
  PCI/ASPM: Add comment about L1 substate latency

 drivers/pci/pcie/Kconfig      |   8 ++
 drivers/pci/pcie/aspm.c       | 291 ++++++++++++++++++++++++++++++++++++++++--
 include/uapi/linux/pci_regs.h |  16 +++
 3 files changed, 302 insertions(+), 13 deletions(-)

-- 
2.8.0.rc3.226.g39d4020


             reply	other threads:[~2017-01-03  6:34 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-03  6:34 Rajat Jain [this message]
2017-01-03  6:34 ` [PATCH 1/6] PCI: Add L1 substate capability structure register definitions Rajat Jain
2017-01-03  6:34 ` [PATCH 2/6] PCI/ASPM: Introduce L1 substates and a Kconfig for it Rajat Jain
2017-01-03  6:34 ` [PATCH 3/6] PCI/ASPM: Read and setup L1 substate capabilities Rajat Jain
2017-01-03  6:34 ` [PATCH 4/6] PCI/ASPM: Calculate and save the L1.2 timing parameters Rajat Jain
2017-01-03  6:34 ` [PATCH 5/6] PCI/ASPM: Actually configure the L1 substate settings to the device Rajat Jain
2017-03-08 18:44   ` James Morse
2017-03-08 22:39     ` Bjorn Helgaas
2017-03-08 23:08       ` Rajat Jain
2017-03-09 11:00         ` James Morse
2017-01-03  6:34 ` [PATCH 6/6] PCI/ASPM: Add comment about L1 substate latency Rajat Jain
2017-02-14 23:45 ` [PATCH 0/6] PCI/ASPM: Add PCIe L1 PM substate support Bjorn Helgaas

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